MODULE 3

MODULE 3: Interrupt mechanism of x86 & Interfacing of chips

Interrupts of 8086- Dedicated Interrupt types- Software interrupts-Hardware interrupts- Priority of interrupts-Programmable
Interrupt Controller (8259)

Organisation and Interfacing of PPI (8255), and Keyboard and display Interface (8279)

Specific Outcomes: MODULE : 3

3.1 To understand the Interrupt mechanism of x86

3.1.1 To describe interrupts of 8086

3.1.2 To explain the different types of interrupts

3.2 To Understand different Interfacing Chips

3.2.1 To describe Programmable Peripheral Interfacing Chip and Interfacing with x86 processor

3.2.2 To explain the importance, organisation, and interfacing of Programmable Interrupt Controller

3.2.3 To describe Keyboard and Display Interface chip and Interfacing with x86 processor

INTERRUPTS OF 8086

 An interrupt is a condition that halts the microprocessor temporarily to work on a different task and then return
to its previous task.

 Interrupt is an event or signal that request to attention of CPU. This halt allows peripheral devices to
access the microprocessor.

 Whenever an interrupt occurs the processor completes the execution of the current instruction and starts the
execution ofan Interrupt Service Routine (ISR) or Interrupt Handler.

 ISR is a program that tells the processor what to do when the interrupt occurs.

 After the execution of ISR, control returns back to the main routine where it was interrupted.

 In 8086 microprocessor following tasks are performed when microprocessor encounters an interrupt:

1. The value of flag register is pushed into the stack. It means that first the value of SP (Stack Pointer) is
decremented by 2 then the value of flag register is pushed to the memory address of stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.

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4. IP is loaded from word location (Interrupt type) * 04.

5. CS is loaded from the next word location.
6. Interrupt and Trap flag are reset to 0.

Interrupt Service Routine

 For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler.

 When an interrupt is invoked, the microprocessor runs the interrupt service routine.

 For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory
locationsset aside to hold the addresses of ISRs is called the interrupt vector table.

 When an interrupt is occurred, the microprocessor stops execution of current instruction. It transfers the content of
programcounter into stack.

 It also stores the current status of the interrupts internally but not on stack. After this, it jumps to the memory
location specified by Interrupt Vector Table (IVT). After that the code written on that memory area will
execute.

Interrupt Vector Table (IVT)

 The interrupt vector (or interrupt pointer) table is the link between an interrupt type code and the procedure that
has beendesignated to service interrupts associated with that code. 8086 supports total 256 types i.e. 00H to FFH.
 For each type it has to reserve four bytes i.e. double word. This double word pointer contains the address of the
procedurethat is to service interrupts of that type.
 The higher addressed word of the pointer contains the base address of the segment containing the procedure.
This baseaddress of the segment is normally referred as NEW CS.

 The lower addressed word contains the procedure’s offset from the beginning of the segment. This offset is
normallyreferred as NEW IP.
 Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will start.

 As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore interrupt pointer table
occupies upto the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low memory.
 The total interrupt vector table is divided into three groups namely,

A. Dedicated interrupts (INT 0…..INT 4)

B. Reserved interrupts (INT 5…..INT 31)

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C. Available interrupts (INT 32…..INT 225)

A. Dedicated interrupts (INT 0…..INT 4):

 INT 0 (Divide Error)-

 This interrupt occurs whenever there is division error i.e. when the result of a division is too large to be stored.
 This condition normally occurs when the divisor is very small as compared to the dividend or the divisor is zero.
 Its ISR address is stored at location 0 x 4 = 00000H in the IVT.

 INT 1 (Single Step)-

 It puts microprocessor in single stepping mode i.e. the microprocessor pauses after executing every
instruction. This is very useful during debugging.

 Its ISR generally displays contents of all registers. Its ISR address is stored at location 1 x 4 = 00004H in
the IVT.
 INT 2 (Non mask-able Interrupt)-

 The microprocessor executes this ISR in response to an interrupt on the NMI (Non mask-able Interrupt) line.
 Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
 INT 3 (Breakpoint Interrupt)-

 This interrupt is used to cause breakpoints in the program. It is caused by writing the instruction INT
03H or simply INT.

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 It is useful in debugging large programs where single stepping is efficient.

 Its ISR is used to display the contents of all registers on the screen. Its ISR address is stored at location 3
x 4 =0000CH in the IVT.
 INT 4 (Overflow Interrupt)-

 This interrupt occurs if the overflow flag is set and the microprocessor executes the INTO (Interrupt on
Overflow) instruction.
 It is used to detect overflow error in signed arithmetic operations.
 Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

B. Reserved interrupts (INT 5…..INT 31):

 These levels are reserved by Intel to be used in higher processors like 80386, Pentium etc. They are not available
to the user.

C. Available interrupts (INT 32…..INT 225):

 These are user defined, software interrupts.

 ISRs for these interrupts are written by the users to service various user defined conditions.

 These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained by the microprocessor
fromlocation n x 4 in the IVT.

TYPES OF INTERRUPTS

 The following image shows the types of interrupts we have in a 8086 microprocessor –

Software Interrupts

 These are instructions that are inserted within the program to generate interrupts.
 There are 256 software interrupts in 8086 microprocessor.
 The instructions are of the format INT type where type ranges from 00 to FF

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
 Some instructions are inserted at the desired position into the program to create interrupts.
 These are 2 byte instructions. IP is loaded from type * 04 H and CS is loaded from the next address give by (type *
04) + 02 H. Some important software interrupts are:

 TYPE 0 (INT 0) corresponds to division by zero(0).

 TYPE 1(INT 1) is used for single step execution for debugging of program.
 TYPE 2 (INT 2) represents NMI and is used in power failure conditions.
 TYPE 3 (INT 3) represents a break-point interrupt.
 TYPE 4 (INT 4) is the overflow interrupt.

 (FOR MORE EXPLANATION REFFER INTERRUPT VECTOR TABLE)

Hardware Interrupts

 Hardware interrupts are those interrupts which are caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
 There are two hardware interrupts in 8086 microprocessor. They are:

1. NMI
 It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin
(INTR)and it is of type 2 interrupt.

 When this interrupt is activated, these actions take place –

 Completes the current instruction that is in progress.

 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.

2) INTR

 The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled
using setinterrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.

 The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the
microprocessor first completes the current execution and sends ‘0’ on INTA pin twice.

 The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor
receives the 8 bit, say X, from the programmable interrupt controller.

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

 These actions are taken by the microprocessor −

 First completes the current instruction.

 Activates INTA output and receives the interrupt type, say X.

 Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack.

 IP value is loaded from the contents of word location X × 4

 CS is loaded from the contents of the next word location.

 Interrupt flag and trap flag is reset to 0.

Difference between Hardware Interrupt and Software Interrupt

SR.N HARDWARE INTERRUPT SOFTWARE INTERRUPT

O.
 1 Hardware interrupt is an interrupt generated from Software interrupt is the interrupt that is
an external device or hardware. generated by any internal system of the
computer.
2 It do not increment the program counter. It increment the program counter.
3 Hardware interrupt can be invoked with some Software interrupt can be invoked with the
external device such as request to start an I/O or help ofINT instruction.
occurrence of a hardware failure.
4 It has lowest priority than software interrupts It has highest priority among all interrupts.
5 Hardware interrupt is triggered by external Software interrupt is triggered by software
hardware and is considered one of the ways to and considered one of the ways to
communicate with the outside peripherals, communicate with kernel or to trigger
hardware. system calls, especially during
error or exception handling.
6 It is an asynchronous event. It is synchronous event.

Priority of interrupt

 As far as the Interrupt Priority in 8086 are concerned, software interrupts (All interrupts except single step,
NMI andINTR interrupts) have the highest priority, followed by NMI followed by INTR.

 Single step has the least priority.

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Programmable Interrupt Controller (8259)

 8259 microprocessor is defined as Programmable Interrupt Controller (PIC) microprocessor.

 There are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively.
 But by connecting 8259 with CPU, we can increase the interrupt handling capability.
 8259 combines the multi interrupt input sources into a single interrupt output.
 Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.

Features of 8259 PIC microprocessor

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can masked individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PIC.
5. Clock cycle is not required.

Pin Diagram of 8259

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PIN Name Description and Purposes

Vcc and Gnd It is the Power supply and ground pins. +5V power supply isused in this chip.

D7-0 For communication with the processor, there are Eight bi-directional data pins.

RD* It is active low-input pin activated by the processor to read the information status from the 8259.

WR* It is an active low-input pin which is activated by the processor to write the control information
to 8259.

CS* For selecting the chip it is used an active low input pin.

A0 An address input pin used along with RD* and WR* which is used to identify the various
command words.

IR0-IR7 There are Eight asynchronous interrupt request inputs. These interrupt requests can be
programmed for level-trigger or edge-triggered mode.

INT A strong active high-output pin which interrupts the processor. Always connected to the INTR
interrupt input of 8085. The INT output is only activated when all the given conditions are
satisfied correctly.

Block Diagram of 8259 PIC microprocessor

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 The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer
Comparator,Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.

1. Databus buffer –

 This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a buffer.

 It takes the control word from the 8085 (let say) microprocessor and transfer it to the control logic of 8259
microprocessor.

 Also, after selection of Interrupt by 8259 microprocessor, it transfer the opcode of the selected Interrupt and address
of the Interrupt service sub routine to the other connected microprocessor.
 The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of
8 bitsdata can be transferred at a time.
2. Read/Write logic

 This block works only when the value of pin CS is low (as this pin is active low).
 This block is responsible for the flow of data depending upon the inputs of RD and WR.
 These two pins are active low pins used for read and write operations.

3. Control logic
 It is the centre of the microprocessor and controls the functioning of every block.
 It has pin INTR which is connected with other microprocessor for taking interrupt request and pin INT for
giving the output.
 If 8259 is enabled, and the other microprocessor Interrupt flag is high then this causes the value of the output
INT pinhigh and in this way 8259 responds to the request made by other microprocessor.
4. Interrupt request register(IRR)

 It stores all the interrupt level which are requesting for Interrupt services.

5. Interrupt service register(ISR)

 It stores the interrupt level which are currently being executed.

6. Interrupt mask register(IMR)

 It stores the interrupt level which have to be masked by storing the masking bits of the interrupt level.
7. Priority resolver

 It examines all the three registers and set the priority of interrupts and according to the priority of the interrupts,
interruptwith highest priority is set in ISR register.
 Also, it reset the interrupt level which is already been serviced in IRR.

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8. Cascade buffer

 To increase the Interrupt handling capability, we can further cascade more number of pins by using cascade
buffer. So, during increment of interrupt capability, CSA lines are used to control multiple interrupt structure.
9. SP/EN (Slave program/Enable buffer) pin

 SP/EN pin is when set to high, works in master mode else in slave mode. In Non Buffered mode, SP/EN pin is
used to specify whether 8259 work as master or slave and in Buffered mode, SP/EN pin is used as an output to
enable data bus.

Interrupt Sequence in an 8086 system

• The Interrupt sequence in an 8086-8259A system is described as follows:

1) One or more IR lines are raised high that set corresponding IRR bits.

2) 8259A resolves priority and sends an INT signal to CPU.

3) The CPU acknowledge with INTA pulse.

4) Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is
reset The 8259A does not drive data during this period.
5) The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to a data bus from
where it is read by the CPU.
6) This completes the interrupt cycle. The ISR bit is reset at the end of the second INTA pulse if automatic end of
interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at
the end of interrupt subroutine.

Command Words of 8259

 The command words of 8259A are classified in two groups

1. Initialization command words (ICW)
2. Operation command words (OCW).
 Initialization Command Words (ICW): Before it starts functioning, the 8259A must be initialized by writing
two to four command words into the respective command word registers. These are called as initialized command
words.
 Operation Command Words(OCW): Once 8259A is initialized using the previously discussed command words
for initialization, it is ready for its normal function, i.e. for accepting the interrupts but 8259A has its own way of
handling the received interrupts called as modes of operation. These modes of operations can be selected by
programming, i.e. writing three internal registers called as operation command words.

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Programmable peripheral interface 8255

 PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its outside world such as
ADC,DAC, keyboard etc.

 It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign different ports as
input or output functions.

Features of 8255A
 The prominent features of 8255A are as follows −
1. 8255 PPI contains 24 programmable I/O pins arranged as 2 8-bit ports & 2 4-bit ports.
2. 8255 PPI contains 3 ports and they are arranged in two groups of 12 pins.
3. It is fully compatible with Intel Microprocessor families.
4. It is also TTL compatible.
5. It has improved DC driving capability.
6. 8255 can operates in 3 modes:
a. Mode 0: Simple I/O.
b. Mode 1: Strobed I/O.
c. Mode 2: Strobed bidirectional I/O

8255 Architecture(block diagram)

 It contains the following blocks:

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I) Data Bus Buffer:

 This is 8-bit bidirectional buffer.
 It is used to interface the internal data bus of 8255 with the external data bus.
 When read is activated, it transmits data to the system data bus.
 When write is activated, it receives data from the system data bus.

II) Read/Write Control Logic:

 It accepts address and control signals from the microprocessor.

 The control signals are read & write while address signals used are A0& A1and CS
 The address bits (A1, A0) are used to select the ports or the control word register as shown


CS A1 A0 SELECTIO
’ N
0 0 0 PORT A

0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control Register
1 X X No Seletion

 CS is connected to address chip select decoder.

 The 8255 operation/selection is enabled/disabled by CS signal.

III) Group A & Group B Control:
 8255 I/O ports are divided into 2 sections: Group A & Group B.
 Group A control block controls Port A & Port C upper i.e. PC7–PC4.
 Group B control block controls Port B & Port C lower i.e. PC3–PC0.
 Each group is programmed through software.
 Group A & Group B controls accepts the control signals from the control word and forwards them to the respective
ports.

IV) Port A, Port B & Port C:

 This are 8-bit bidirectional ports.
 They can be programmed to work in the various modes as follows:
 Group A control block controls Port A & Port C upper i.e. PC7–PC4.
 Only Port C can also be programmed to work in Bit Set/Reset Mode to manipulate its individual bits.

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Modes of operation
 There are two different modes of 8255. These modes are:
 Bit Set Reset (BSR) Mode

 Input/ Output Mode

a) Bit Set Reset (BSR) Mode:

 This mode is used to set or reset the bits of the Port-C only. For BSR mode always D7 will be 0. The control
register islooking like this:

 The (D3, D2, D1) will be 000 to 111.

 In this mode it affects only one bit of Port C at a time. When user set the bit, it remains set until user unset it.
The user needs to load the bit pattern in control register to change the bit.

b) Input/ Output Mode:

 This mode is selected when the D7 bit of the control register is 1.

 This mode has also three different modes. These modes are Mode 0 and Mode 1 and Mode 3.

1) Mode 0 – Simple or basic I/O Mode

 In this mode all of the ports A, B and C can be used as input or output mode. The outputs are
latched, but inputs are not latched. This mode has interrupt handling capability.
2) Mode 1 – Handshake or Strobed I/O
 In this mode the Port A and Port B can be used as input or output ports, the port C are used for handshaking.
 In this mode the inputs and outputs are latched. This mode also has the interrupt handling
capability, andsignal control to match the speed of CPU and IO devices.

3) Mode 3 – Bidirectional I/O

 In this mode only Port A can work, and port B can either be in mode 0 or mode 1, and the port C are
used for handshaking.
 In this mode the inputs and outputs are latched. The control register is looking like below in this mode:

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Bits Function

D7 1 for IO mode and 0 for BSR mode

D6 & D5 These are used to set port A mode. for 00, it is m0 mode, for 01, it is m2
mode and 10 or 11, it is m2 mode.

D4 1 when port A is taking input, 0 when port A is sending output.

D3 1 when higher nibble of port C is taking input, and 0 when higher nibble is
sending output.

D2 It tells the mode of Port B. For 0, it is m0 mode, and for 1, it is m1 mode.

D1 1 when port B is taking input, 0 when port B is sending output.

D0 1 when lower nibble of port C is taking input, and 0 when lower nibble is
sending output.

Keyboard and display Interface (8279)

 8279 programmable keyboard/display controller is designed by Intel that interfaces a keyboard with the CPU.

 The keyboard first scans the keyboard and identifies if any key has been pressed. It then sends their relative response
of the pressed key to the CPU and vice-a-versa.
 The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt mode, the processor is
requestedservice only if any key is pressed, otherwise the CPU will continue with its main task.

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 In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether any key is pressed or not
with keypressure.

How Does 8279 Keyboard Work?

 The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the key-codes.

 These key-codes are de-bounced and stored in an 8-byte FIFO RAM, which can be accessed by the CPU.

 If more than 8 characters are entered in the FIFO, then it means more than eight keys are pressed at a time. This is
when the overrun status is set.

 If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else the CPU checks the
status inpolling to read the entry.

 Once the CPU reads a key entry, then FIFO is updated, and the key entry is pushed out of the FIFO to generate
space for new entries.

Architecture of 8279

a) I/O Control and Data Buffer

 This unit controls the flow of data through the microprocessor.

 It is enabled only when D is low.
 Its data buffer interfaces the external bus of the system with the internal bus of the microprocessor. The pins A0,
RD, and WR are used for command, status or data read/write operations.

b) Control and Timing Register and Timing Control

 This unit contains registers to store the keyboard, display modes, and other operations as programmed by the
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CPU. Thetiming and control unit handles the timings for the operation of the circuit.

c) Scan Counter

 It has two modes i.e. Encoded mode and Decoded mode.

 In the encoded mode, the counter provides the binary count that is to be externally decoded to provide the scan
lines for the keyboard and display.

 In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1
out of 4scan on SL0-SL3.

d) Return Buffers, Keyboard Debounce, and Control

 This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces the key entry.

 In case, the same key is detected, then the code of that key is directly transferred to the sensor RAM along with
SHIFT& CONTROL key status.

e) FIFO/Sensor RAM and Status Logic

 This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key is entered into the
RAMas per their sequence.

 The status logic generates an interrupt request after each FIFO read operation till the FIFO gets empty.

 In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded with the status of
their corresponding row of sensors into the matrix.

 When the sensor changes its state, the IRQ line changes to high and interrupts the CPU.

f) Display Address Registers and Display RAM

 This unit consists of display address registers which holds the addresses of the word currently read/written by the
CPUto/from the display RAM.

8279 − Pin Diagram

 The following figure shows the pin diagram of 8279 –

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a) Data Bus Lines, DB0 - DB7

 These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.

b) CLK

 The clock input is used to generate internal timings required by the microprocessor.

c) RESET

 As the name suggests this pin is used to reset the microprocessor.

d) CS Chip Select

 When this pin is set to low, it allows read/write operations, else this pin should be set to high.

e) A0

 This pin indicates the transfer of command/status information. When it is low, it indicates the transfer of data.

f) RD, WR

 This Read/Write pin enables the data buffer to send/receive data over the data bus.

g) IRQ

 This interrupt output line goes high when there is data in the FIFO sensor RAM.

 The interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM further contains
any key- code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU.

h) Vss, Vcc

 These are the ground and power supply lines of the microprocessor.

i) SL0 − SL3

 These are the scan lines used to scan the keyboard matrix and display the digits.

 These lines can be programmed as encoded or decoded, using the mode control register.

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j) RL0 − RL7

 These are the Return Lines which are connected to one terminal of keys, while the other terminal of the
keys is connected to the decoded scan lines. These lines are set to 0 when any key is pressed.

k) SHIFT

 The Shift input line status is stored along with every key code in FIFO in the scanned keyboard mode. Till it is
pulledlow with a key closure, it is pulled up internally to keep it high

l) CNTL/STB - CONTROL/STROBED I/P Mode

 In the keyboard mode, this line is used as a control input and stored in FIFO on a key closure.

 The line is a strobe line that enters the data into FIFO RAM, in the strobed input mode.

 It has an internal pull up. The line is pulled down with a key closure.

m) BD

 It stands for blank display. It is used to blank the display during digit switching.

n) OUTA0 – OUTA3 and OUTB0 – OUTB3

 These are the output ports for two 16x4 or one 16x8 internal display refresh registers.

 The data from these lines is synchronized with the scan lines to scan the display and the keyboard.

Operational Modes of 8279

 There are two modes of operation on 8279 − Input Mode and Output Mode.

a) Input Mode

 This mode deals with the input given by the keyboard and this mode is further classified into 3 modes.

 Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either encoded or decoded

scans. Inthe encoded scan, an 8×8 keyboard or in the decoded scan, a 4×8 keyboard can be interfaced. The code
of key pressedwith SHIFT and CONTROL status is stored into the FIFO RAM.

 Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the processor using either encoder
or decoder scans. In the encoder scan, 8×8 sensor matrix or with decoder scan 4×8 sensor matrix can be
interfaced.

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 Strobed Input − In this mode, when the control line is set to 0, the data on the return lines is stored in the FIFO
byte by byte.

b) Output Mode

 This mode deals with display-related operations. This mode is further classified into two output modes.

 Display Scan − This mode allows 8/16 character multiplexed displays to be organized as dual 4-bit/single
8-bitdisplay units.

 Display Entry − This mode allows the data to be entered for display either from the right side/left side.

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MODULE 3

MODULE 3: PREVIOUS YEAR QUESTIONS

SHORT ANSWER (2 marks and 6 marks)

1. Write the priority of interrupts .

2. Explain the operating modes of 8255.
3. Define interrupt.
4. Differentiate software and hardware interrupt.
5. Draw and explain interrupt vector table.
6. Write two major interfaces provided by 8279.
7. Define interrupt service routine and interrupt vector. draw the format of interrupt vector in 8086.
8. List the internal registers in 8259 and explain how interrupts are handled in 8259.
9. Write the order of priority of interrupts in 8086.
10. What are the two types of control words in 8259.
11. How is an interrupt different from call.
12. Write the hardware interrupt of 8086.
13. What are the application of 8279 IC.
14. Describe the control register format for BSR mode operation of 8255.
ESSAY QUESTIONS (8 marks and 7 marks)

1. Explain dedicated interrupt in 8086.

2. Describe interrupt vector table.
3. Draw the block diagram of 8279 with keyboard and display.
4. Explain the functional blocks in 8279.
5. Draw and explain the internal architecture of 8259 programmable interrupt controller.
6. List and explain operating modes of 8255 PPI.
7. Write about scan section of 8279.
8. Describe hardware and software interrupts.
9. Explain the steps in processing an interrupt request.
10. Draw the internal diagram of 8255 and briefly explain each block.
11. Write interrupt response of 8086.
12. How interrupt vectors are stored in 8086.

MICROPROCESSORS AND INTERFACING Page 20