Lecture 12

Interrupts
An interrupt is an external or internal event that interrupts the
microprocessor to inform it that a device needs its service.

The program which is associated with the interrupt is called the

Interrupt Service Routine (ISR)

Steps in executing an interrupt

Finish current instruction and saves the IP on stack.

Jumps to a fixed location in memory depend on type of interrupt
Starts to execute the interrupt service routine until RETI (return
from interrupt)
Upon executing the RETI the microprocessor returns to the place
where it was interrupted. Get pop IP from stack 1
Lecture 12 Interrupt Vectors

Each interrupt has a specific place in code memory where program

execution (interrupt service routine) begins.

 A real mode interrupt vector is 4 bytes in length and contains the

segment and offset address of the interrupt service procedure

 A protected mode interrupt vector is 8 bytes in length and contains the

selector and 32-bit offset address of the interrupt service procedure.

 In a protected mode the interrupt descriptor table (IDT) is used to

,
implement an interrupt vector table.

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Lecture 12
Interrupt Vectors (Real mode)

The first 1024 bytes of memory (addresses 00000 – 003FF)

always contain the Interrupt Vector Table (IVT).
Each of the 256 vectors requires four bytes—two for segment,
two for offset

Physical address Interrupt Number

03FC Type 255

4*X Type X

0008 Type 2

0004 Type 1

0000 Type 0

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Lecture 12
Interrupt Vectors
Table
(Real mode)

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Interrupt Vectors Table
(Protected Mode)

 The protected mode uses interrupt descriptor table IDT &

(interrupt descriptor table register) IDTR
 IDTR contain the base address of the descriptor table and its limit
 Each of the IDTs tables can hold only 256 entries, each of 8 bytes
in size.
 An IDT : In 80386 processor, when interrupt occurs, the interrupt
number (0-255) is used as index into IDT.

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Interrupt Vectors Table
(Protected Mode)
 In order to find the interrupt services address, it is required to find
the start address of the code segment where interrupt services
resides. the segment selector in interrupt descriptor is used to index
into GDT/LDT. Using base address in GDT/LDT and the offset in
interrupt descriptor, the start of the interrupt service can be
allocated.

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Lecture 12
Interrupts
Type 0 to Type 32 have predefined functions.
Type 0: invokes by when there is an attempt to divide a number by zero or
result from a division overflows
Type 1: specifically for implementation of single-stepping instructions for
program tracing. The trap flag (TF), must be set to 1. After execution of each
instruction, microprocessor jumps to physical location 00004 to fetch CS:IP
of the interrupt service routine.
Type 2: for NMI. When the NMI pin is activated by a high (5V) signal, the
CPU jumps to physical memory location 00008 to fetch the CS:IP of the ISR
routine associated with NMI.
INT 03: for the implementation of breakpoints in software engineering. A
breakpoint is used to examine CPU and memory after the execution of a
group of instructions.
Type 4: (Interrupt on Overflow) instruction. If instruction INTO is placed
after a signed number arithmetic or logic operation such as IMUL or ADD,
the CPU will activate Type 4 if OF = 1. If OF = 0, INTO is bypassed, acting
as a NOP (no operation) instruction. 7
Lecture 12 Interrupts

 Type 4: The BOUND instruction compares a register with boundaries

stored in the memory. If the contents of the register are greater than or
equal to the first word in memory and less than or equal to the second
word, no interrupt occurs. If the contents of the register are out of bounds,
a type 5 interrupt ensues
 Type 6: An invalid opcode interrupt occurs whenever an undefined
opcode is encountered in a program.
 Type 7: The coprocessor not available interrupt occurs when a
coprocessor is not found in the system. If an ESC or WAIT instruction
executes and the coprocessor is not found, a type 7 exception or interrupt
occurs, is used to emulate a coprocessor
 Interrupts Type 32 to Type 255 can be used for either software
or hardware interrupts.

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Lecture 12

Example: Find the physical addresses in the interrupt vector table

associated with INT 12h?

The physical addresses for INT 12h are 00048-00048h since 4x12h= 48H
Software interrupts
Software interrupts are triggered with the INT instruction and
IRET
INT does the following:
Pushes flag register (PUSHF)
Pushes the current CS and IP
Far jumps to [0000:(4*Interrupt vector type)]
Usually clears the interrupt flag disabling the interrupt system
IRET does the following
Pops flag register
Performs a far return
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Lecture 12

Software interrupt Instruction are: INT, INTO, INT 3, and

BOUND
INT n Instruction:
Special cases:
 n = 1: Single step (trap)
Enabled if TF (Trap flag) bit in Flags is set
 n = 3: INT 3 (Breakpoint)
 n = 4: INTO (Overflow)
 n = 5: BOUND (Check limits)

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Lecture 12

Conditional:
INTO (type 4): on Overflow (the OF flag bit)
BOUND (type 5): on the result of comparing the contents of a
register with the contents of two successive words in memory,
e.g. BOUND AX, DATA
Causes interrupt type 5 if AX contents are outside the range
specified by the 4 bytes
i.e., [AX] < {[DATA], [DATA+1]} or [AX] > {[DATA+2],
[DATA+3]}

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Lecture 12

Unconditional:
 INT n: Executes the interrupt with the vector type n
Instruction takes 2 bytes: a byte for the opcode and a byte for n
e.g. INT 80H  Start of the 4-byte vector address = 4 x 80H =
200H (200H – 203H)
 INT 3: is a special case of INT n which fits into one byte
only. Useful in inserting a break point in the software for
debugging purposes

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Lecture 12
Hardware interrupts
Hardware interrupt are triggered with INT or NMI signals
INTR is a MPU input signal, which can be masked & unmasked
through use CLI and STI.
NMI (Non-Maskable Interrupt), is an input signal into the MPU,
cannot be masked and unmasked. Power failure interrupts to
processor (NMI).
Interrupt enabling/disabling

You can enable/disable all mask able hardware interrupts

The CLI instruction disables all mask able hardware interrupts
The STI instruction enables all mask able hardware interrupts

Some hardware situation that needs the processor’s attention

 A key has been pressed
 A timer has expired
 A network packet has arrived
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Lecture 12
The 80x86 interrupt interface

INT Request (INTR)

80x86 INT Acknowledge (INTA)

processor Some device
Data bus

Device generates request signal

MPU response by sending INTA
Device supplies interrupt vector number on data bus
Processor completes the execution of current instruction and
executes ISR corresponding to the interrupt vector number on the
data bus

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Lecture 12

There are typically two INTA pulses generated for the following reasons:

 The first INTA pulse informs the interrupting device that the
processor is ready to receive the Interrupt Vector Type Number
 The second INTA pulse is generated by the processor to latch the
Interrupt Vector Type Number from the data bus.

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Lecture 12

Expanding the Interrupt Structure

Will use hardware/software to expand the number of interrupt inputs

that can be connected to the processor via the INTR input:

1. Hardware: Additional NAND gate for 7 interrupts

2. Software: Daisy chaining of interrupts
3. A Programmable Interrupt Controller (PIC) 8259A - for up to 64
interrupts

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Lecture 12
1. Additional NAND for 7 interrupts

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Lecture 12

2. Daisy Chaining of Interrupts by Software

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Lecture 12

3. Programmable Interrupt Controller (8259 PIC)

0
1
2
Interrupt outputs
3
from peripheral
4
devices
8259 5
PIC 6
7

INTR
INTA 8086
INT#

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Lecture 12
Pin Diagram of 8259

D0–D7: The bidirectional data

connections are normally connected to
the data bus on the microprocessor.
IR0–IR7 Interrupt request inputs are
used to request an interrupt and to connect
to a slave in a system with multiple
8259As.
WR: The write input connects to IOWC
RD: The read input connects to the
IORC.
INT: The interrupt output connects to
the INTR.
INTA: Interrupt acknowledge

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Lecture 12
Pin Diagram of 8259

A0: The A0 address input selects different command words within

the 8259A.
CS: Chip select enables the 8259A for programming and control.
SP/EN: Slave program/enable buffer is a dual-function pin. When
the 8259A is in buffered mode, this is an output that controls the data
bus transceivers. When the 8259A is not in the buffered mode, this
pin programs the device as a master (1) or a slave (0).
CAS0–CAS2 The cascade lines are used as outputs from the master
to the slaves for cascading multiple 8259As in a system. These pins
are outputs for a master 8259A and inputs for a slave 8259A.
IR0 to IR7: interrupt request - hardware interrupts

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