BCSE205L

Computer Architecture and Organization

Module 3 – Instruction Sets and Control Unit

Dr. P.Keerthika
Associate Professor
School of Computer Science and Engineering
Vellore Institute of Technology, Vellore
Computer Instructions: Instruction sets
• Instruction
• Is a statement by which the operation of CPU is determined.
• These instructions referred as “Machine instructions or computer Instructions”

• Elements of Machine instruction

• Operation code
• Source operand reference
• Result operand Reference
• Next instruction reference
Computer Instructions: Instruction sets
• Program
• is sequence of instructions which operates on data to perform certain tasks.
• Instruction
• Is a statement by which the operation of CPU is determined
• Instruction Cycle
Instruction Cycle: State Diagram
Instruction Set Architecture
• Instruction Set Architecture (ISA) - defines how the CPU is controlled by the
software
• ISA acts as an interface between the hardware and the software, specifying both
what the processor is capable of doing as well as how it gets done
• It defines the supported data types, the registers, how the hardware manages main
memory, key features (such as virtual memory), which instructions a
microprocessor can execute, and the input/output model of multiple ISA
implementations
Instruction formats
• Each instruction is represented by sequence of bits
• The instruction is divided into two fields
• Opcode field
• Operand field
• This operand field further divided into one to four fields.
• This layout of the instruction is known as the “Instruction Format”
• Simple instruction format
Instruction Set category
• Instruction Set is categorized into types based on
• Operation performed
• Number of operand addresses
• Addressing modes.
Instruction Set category
• Based on Operation being performed
• Data movement/Data Transfer  Move data from a memory location or register to
another memory location or register without changing its form.
• Memory - LOAD, STORE, MOV
• I/O Instructions - IN, OUT
• Data processing/Data Manipulation Arithmetic and logic (ALU) instructions -
Changes the form of one or more operands to produce a result stored in another
location
• Arithmetic - Add, Sub, MUL, DIV
• logic Instructions - AND, OR,
Instruction Set category
• Based on Operation being performed
• Flow Control/Program control  Any instruction that alters the normal flow of
control from executing the next instruction in sequence
• Conditional
• JNZ, JZ
• Un Conditional
• Jump
Instruction Set category
• Based on Number of operand addresses
• Instruction Set categorized into four categories based on number of operand
address in the instruction.
• 4-Address Instruction
• 3-Address Instruction
• 2-Address Instruction
• 1-Address Instruction
• 0-Address Instruction
Instruction Set category
Three Address Instruction
Example:

Two Address Instruction

Instruction Set category
One Address Instruction

Zero Address Instruction

(Don’t use address field for
instruction
Calculation of Memory traffic
• Assumptions
• 24-bit memory address (3 bytes)
• 128 instructions (7 bits rounded to 1 byte)
Memory Required to store an Instruction: 5 x 3 bytes = 15 Bytes
4 – address Instruction Design

• Because of the large instruction word size and number of memory

accesses ,the 4- address machine and instruction format is not seen in
the machine design.

• Although the 4-address structure is used internally in some

implementations of computer control units. This kind of controller
implementations is known as microcoded Control.
Memory Required to store an Instruction: 4 x 3 bytes = 12 Bytes
3 – address Instruction Design
3-Address instruction:
• Address of next instruction kept in processor state register—the PC (Except for explicit Branches/Jumps)
• Rest of addresses in instruction
• This Instruction will require 3X3+1= 10 bytes to encode a 3-address ALU instruction.
The number of memory access are required for a 3-address instruction:
• Four words will be transferred to the CPU when the instruction itself is fetched.= 4
• Then the two words representing the operands themselves need to be fetched into the CPU = 2
• And after the addition has been performed, the result needs to be written back to memory = 1 Total =07
2 – address Instruction Design
2-address Instruction :
• Result overwrites Operand 2
• Needs only 2 addresses in instruction but less choice in placing data
• This Instruction will require 2X3+1= 7 bytes to encode a 2-address ALU instruction.
The number of memory access are required for a 2-address instruction:
• Three words will be transferred to the CPU when the instruction itself

is fetched. = 3
• Then the two words representing the operands themselves need to be fetched into he CPU and after the addition
has been performed, Result overwrites Operand =3
• Total= 06
• add Op1Addr Op2Addr
Memory Required to store an Instruction: 2 x 3 bytes = 06 Bytes

Result stored in Accumulator – Hence No Memory access required

1 – address Instruction Design

1-address Instruction :
• Special CPU register, the accumulator, supplies 1 operand and stores result
• One memory address used for other operand
• Need instructions to load and store operands:
• LDA OpAddr

• STA OpAddr

• This Instruction will require 1X3+1= 4 bytes to encode a 1-address ALU instruction

The number of memory access are required for a 1-address instruction:

• Two words will be transferred to the CPU when the instruction itself is fetched = 2
• Then the one word representing the operand itself need to be fetched into the CPU register and the accumulator, supplies 1 operand and stores
result = 1
• Total=03
Fetch Instruction – 2 cycles
Fetch Operand – 1 cycle
(Uses stack to store when PUSH & hence no store in memory

Fetch Instruction – 1 cycles, Fetch Operand & Execute – 0 cycle

(Uses stack to perform ADD & store the result in stack when ADD & No store in memory
Comparisons
Instruction Memory Memory M/As to fetch an M/As to Memory
Type To Store To Encode Instruction Execute an Traffic
in Bytes in Bytes Instruction

4-address 5 x 3 = 15 1+(4 x 3) = 13 5 3 5+3=8

3-Address 4 x 3 = 12 1+(3 x 3) = 10 4 3 4+3=7

2-Address 3 x 3 = 09 1+(2 x 3) = 07 3 3 3+3=6

1-Address 2 x 3 = 06 1+(1 x 3) = 04 2 1 2+1=3

0-Address 1 x 3 = 03 1+(0 x 3) = 01 1 (ADD..) (or) 0 (ADD..) (or) 1+0=1

2 –(PUSH..POP) 1 –(PUSH..POP)
Problems – Example1
• Evaluate a = (b+c)*d – e in 3-, 2-, 1-, 0- address machines and
compute the memory traffic. Assume 24 bit memory address and one
byte opcode.
3-address 2-address 1-address 0-address
Memory traffic for 3-address
Machine: 7 * 3 = 21(Maximum)
add a,b,c load a,b Load b Push b
Memory traffic for 2-address
mul a,a,d Add a,c Add c Push c
Machine: 6 * 4 = 24(Maximum)
sub a,a,e Mul a,d Mul d Add
Sub a,e Sub e Push d Memory traffic for 1-address
Machine: 3 * 5 = 15(Maximum)
Store a Mul
Push e Memory traffic for 0-address
Sub Machine: 3 * 5 + 3 = 18 (Maximum)
Pop a
Memory Memory M/As to M/As to Memory
Three-address to Store to encode Fetch Execute Traffic

add a, b, c ab+c 4*3=12 1+(3*3)=10 4 3 4+3=7

mpy a, a, d aa*d
4*3=12 1+(3*3)=10 4 3 4+3=7
sub a, a, e aa-e
4*3=12 1+(3*3)=10 4 3 4+3=7

36 30 12 9 21

Two-address
Memory Memory M/As to M/As to Memory
load a, b ab
to Store to encode Fetch Execute Traffic
add a, c aa+c
3*3=9 1+(2*3)=7 3 2 3+2=5
mpy a, d aa*d
sub a, e aa-e 3*3=9 1+(2*3)=7 3 3 3+3=6

3*3=9 1+(2*3)=7 3 3 3+3=6

3*3=9 1+(2*3)=7 3 3 3+3=6

36 28 12 11 23
Memory Memory M/As to M/As to Memory
One-address to Store to encode Fetch Execute Traffic
2*3=6 1+(1*3)=4 2 1 2+1=3
load b Accb
2*3=6 1+(1*3)=4 2 1 2+1=3
add c AccAcc+c
2*3=6 1+(1*3)=4 2 1 2+1=3
mpy d AccAcc*d
2*3=6 1+(1*3)=4 2 1 2+1=3
sub e AccAcc-e
2*3=6 1+(1*3)=4 2 1 2+1=3
store a aAcc
30 20 10 5 15

Zero-address Memory Memory M/As to M/As to Memory

to Store to encode Fetch Execute Traffic
push b 2*3=6 1+(1*3)=4 2 1 3
2*3=6 1+(1*3)=4 2 1 3
push c
1*3=3 1 1 0 1
add
2*3=6 1+(1*3)=4 2 1 3
push d
1*3=3 1 1 0 1
mpy
2*3=6 1+(1*3)=4 2 1 3
push e
1*3=3 1 1 0 1
sub
2*3=6 1+(1*3)=4 2 1 3
pop a
39 23 13 5 18
Problems – Example 2
Assume 24 bit memory address and one byte opcode.
Practice problems
• Evaluate the expression a = b - c * d and compute memory traffic for 4, 3, 2, 1,and 0 address machine.
Assuming that addresses are 16 bits, data values are 16 bits, opcodes are 8 bits and 1 byte word length.

• Develop a comparative table for the performance parameters such as memory to store, memory to encode,
M/As to fetch , M/As to execute and total memory Traffic for 4-,3-,2-,1-,0- address machine instructions.

• Consider the following specifications: Memory word size is 1 byte, Memory/register Address size is 2byte,
Opcode size is 1 byte.

i. Write an appropriate assembly language programming using 3-Address, 2-Address, 1-Address and 0-
address machine instructions for the following expression ( with registers & without registers). Assume
that all are integer operations.
X= (A / B + C * D) / (D * E - F + C / A) + G

ii. Compute various performance factors such as memory to store a program, memory to encode a whole
program, Memory access to fetch & execute and memory traffic.