The Wayback Machine - https://web.archive.org/web/20220428103639/https://github.com/topics/processor-architecture
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Processor Counter Monitor
GPGPU microprocessor architecture
CoreFreq is a CPU monitoring software designed for the 64-bits Processors.
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
SST Architectural Simulation Components and Libraries
Super scalar Processor design
Updated
Sep 7, 2014
Verilog
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
Updated
Jun 19, 2021
VHDL
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
A collection of my cources, lectures, articles and presentations
Modular Graphical Simulator for Teaching Microprogramming
Updated
Feb 16, 2022
Java
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
Single Bus Processor - Summer Project 2016
Updated
Apr 8, 2018
Verilog
Flexible functional simulator and assembler for user-defined architectures
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
Updated
Jan 28, 2019
Verilog
CS 552 term project : functional design of a microprocessor called the WISC-SP13
Updated
May 14, 2017
Assembly
💻 MIPS Pipeline Processor simulator
Updated
Jun 16, 2020
Python
Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
Updated
Nov 28, 2019
Verilog
An 8-bit processor in VHDL based on a simple instruction set
A Three Stage Pipeline 16-bit processor implemented in Verilog
Updated
Mar 19, 2017
Verilog
Open source ISA | Useful in co-processors/CISC add-ons, and limitless code compatibility
MIPS Pipelined CPU simulation using VHDL language
Updated
May 30, 2020
VHDL
Implementation of a soft-core CPU and an assembler
Updated
Jan 19, 2021
VHDL
Continuation of a functional Tomasulo out-of-order processor, with a cache prefetcher and replacement policy. Implements most of the RV32I ISA.
Updated
Dec 6, 2021
Python
Sextium® III processor implemented in Verilog
Updated
Aug 20, 2018
Verilog
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For those who want the fastest possible simulation, and do not care about any form of datapath visualization, there should be an option to select an ISA simulator processor model.
This processor model, while complying with the ProcessorInterface, will in VSRTL be implemented as a "black box" - in other words, pure C++ logic.