©) INSTITUTE OF SCIENCE & TECHNOLOGY Deemed tobe University w/s3of UGC At, 156 ANALOG AND DIGITAL CIRCUITS Course Code: 18AUE211J Unit 4: Combinational Circuits Dr. CARUNAISELVANE.C Assistant Professor Automobile Engineering Department SRM Institute of Science and Technology.Introduction to Combinational Circuits * Combinational Logic Circuits : memoryless digital logic circuits whose output at any instant in time depends only on the combination of its inputs. A Pp Matiple J 5 Combinational {> * | one or More Inputs Logic Circuit yf Outputs Output = Finpe *» Made up from basic logic NAND, NOR or NOT gates that are “combined” or connected together to produce more complicated switching circuits. Loge Gates A Digital g Inputs ot Boolean Expression Q=B). ABC ‘Output (a) Logie Diagram Typical Truth Table [email protected]‘7 Novernber 2022 [email protected] 3* Binary Addition: when adding binary numbers, a carry out is generated when the “SUM” equals or is greater than two (1+1) and this becomes a “CARRY” bit for any subsequent addition being passed over to the next column for addition and so on. 0 0 1 1 40 41 40 a1 0 1 1 (carry) 1-0 * Operation of a simple adder requires: two data inputs producing two outputs, the Sum (S) of the equation and a Carry (C) bit as shown, a— [SUM s ral Half s Inputs Aude Output 8 oot [ our > oo"* Binary Addition: when adding binary numbers, a carry out is generated when the “SUM” equals or is greater than two (1+1) and this becomes a “CARRY” bit for any subsequent addition being passed over to the next column for addition and so on. 0 0 1 1 40 41 40 a1 0 1 1 (carry) 1-0 * Operation of a simple adder requires: two data inputs producing two outputs, the Sum (S) of the equation and a Carry (C) bit as shown, a— [SUM s ral Half s Inputs Aude Output 8 oot [ our > oo"% % RY % Sum of their binary addition resembles that of an Exclusive-OR Gate. Exclusive-OR gate will only produce an output “1” when “EITHER” input is at logic “1”. We need an additional output to produce the carry bit when “BOTH” inputs A and B are at logic “1”. One digital gate that fits the bill perfectly producing an output “1” when both of its inputs A and B are “1” (HIGH) is the standard AND Gate. stedu.in 2 input OR Gate ao iz Boy 2 input AND GatePama oy * By combining the Exclusive-OR gate with the AND gate results in a simple digital binary adder circuit known commonly as the “Half Adder” circuit. = For the SUM bit: SUM = A XORB=Ae®B = For the CARRY bit: CARRY = A AND B = A.B [email protected] 7@SRM * A Full Adder Circuit: “» The main difference between the Full Adder and Half Adder is that a full adder has three inputs. * The same two single bit data inputs A and B as before plus an additional Carry-in (C-in) input to receive the carry from a previous stage. s—| Full a Adder | canny Inputs Full Adder Full Binary Adder Logic Diagram [email protected] 8A Full Adder Ci “Boolean expression for a full adder is as follows. = For the SUM (S) bit: SUM = (A XOR B) XOR Cin = (A B) © Cin = For the CARRY-OUT (Cout) bit: CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ® B) afafolo fa atafafafa 7 November 2022 [email protected] 9“ n-bit Binary Adder: To add together two n-bit numbers, then n number of 1-bit full adders need to be connected or “cascaded” together to produce what is known as a Ripple Carry Adder. “carry signals produce a Ag-Ag= Ist4-bit number MsB B:-B:= 2nd 4-bit number LsB “ripple” effect through As Bs fe Be Ay By Aa Bs the binary adder from 1] 1| 1 | right to left, (Least con (| -, .. .. (= 7 Significant Bit, LSB to “Voie demunipioxer 8 oe [email protected] 20Parity Generator and Parity Chec Majority of modern communication is Digital in nature i.e., it is a combination of 1’s and 0's. The digital data is transmitted either through wires (in case of wired communication) or wireless. Even in an advanced mode of communication, there will be errors while transmitting data (due to noise). The simplest of errors is corruption of a bit i.e., a 1 may be transmitted as a 0 or vice-versa. To confirm whether the received data is the intended data or not, we should be able to detect errors at the receiver. Parity Generator and Parity Checker. [email protected] auParity Generator and Parity Check Parity Bit: Parity generating technique: most widely used error detection techniques for the data transmission. Parity Bit is added to the word containing data in order to make number of 1s either even or odd. The message containing the data bits along with parity bit is transmitted from transmitter to the receiver. At the receiving end, the number of 1s in the message is counted and if it doesn’t match with the transmitted one, it means there is an error in the data. Thus, the Parity Bit it is used to detect errors, during the transmission of binary data. 1 oF 2 stop bis 7 November 2022 [email protected] Sarlbi aga code Farlly tit mM io) | ~|01000001|P | ~~ 8 bits including pari 7 bits of data (count of 1-bits) sean cml ‘9000000 0 cocgecce | aoa00001 a eee SS [crea viens smo1001 | 4 1010010 11010011 [ara 7 viiit | iio 2Parity Generator and Parity Check * Parity Generator: Combination circuit at the transmitter, it takes an original message as input and generates the parity bit for that message and the transmitter in this generator transmits messages along with its parity bit. Parity Generator o—— Even Parity Generator (Odd Parity Generator ] bits inciiaing panty Tbits of data | (count of 1-bits) Parl ici even odd ote ‘000000 jo000000 00000001 [ola fol afar fren rate 2 0 (oda parity soro001 | 3 10100011 10100010 101001 | z 44010010 1010011 party bit = 1 (incase of even parity setting) parity bit =O {in ease of odd parity setting) 7 | anne amttitt 11111110 7 November 2022 [email protected] BParity Generator and Par “Even Parity Generator: S-bit message Even parity bit generator (P) A 8 ic y 0 0 0 0 o o 1 1 o 1 0 1 0 1 1 o 1 ° o 1 1 ° 1 o 4 1 ° 0 1 1 1 1 XOR For 2-Bit Sum And 3-Bit Sum P-ABC+ABC+ABC+ABC =) =3@C+BO)+AGC+BO) —)>-« =ABOO+AB OC) P=AGBEC [email protected] 24Parity Generator and Parity Chec “ Odd Parity Generator: ‘3-bit massage ‘Odd parity bit generator (P) v He Ke | Je Jo lo Jo |> nn Jo Jo |e |» lo Jo Jo so |e Jo |e Jo |e Jo Jo lo |e Jo fm Jo fo [a (Odd Parity Generator Logic Circuit P=A®(BeC) @electronics Hub [email protected] 2s“Parity Checker: Combination circuit at the receiver, it takes an original message as input and checks the parity bit for that message 1 [aa nonng aay, Tits of data (count of t-bits) > SINS PATHY. ic even odd i ae ae — ee even party 9900000 ‘00900000 | oo000001 o|t|ol4]o ber a [000000 | 0 [rowooor 3 sor00011 10100010 | soto | a 41010010 14010011 parity bit = (in case of even party setting) parity bit = 0 ( in case of odd parity setting) Lon | 7 anti t1ittt0 7 November 2022 [email protected] 26@SRM y Check “Even Parity Checker: Sacierecalucsnenaes Parity error check C, Logic Circuit Of Even Parity Checker =D —=D— s=pt » =] 7 = » = = Parity Generat lela elle le |efolelelolelelelo|> nln |eHlolelelo|elH|e|-lololelo|s ple lolo|n|elolofn|elololn|+lolola Hlolmlo|nlolmle|elo|Hfolmlo|n fo) eo) mol folo|m|nlolo|n ole |u lo PEC- A B(CP+CP)+ A B(C P+CP)+AB(C P+CP )+AB(C P +CP) =A B(CoP)+ A B(COP )+AB(COP)+AB (COP ) ~ (A B+AB)(COP)+(A B+AB )(COP ) ‘7 Novernber 2022 = (A®B)SCSP) [email protected] nnParity Generator and Parity Chec “ Odd Parity Checker: ‘abit received message ry B c Pp Parity error check C,, Logic Circuit Of Odd Parity Checker o | o | o | o 2 o |e | «| a ° —p— sc o | o [a [oa a a) > = Lo 1 ° ° 0 ofa foo [4 1 =— o | 31 [110 1 gerne ne ee ° a [0 | 010 0 te > es 2 7] 0 [170 1 te >a ps ° + | 31 [°° 2 2]. pe [2 ° 1 | 1 [31 0 ° ta pa be 2 PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR P) [email protected] 28circuits. Binary to/from Gray Code: Since the BCD code has only 4 bits, a total of 9 BCD digits have been considered. The output is unpredictable for other input combinations. From the minterms of each output G3, G2, Gi, GO, the karnaugh map is implemented to simplify the function @SRM Code Converters Code converter: convert one type of binary code to another. Types of binary codes: BCD code, gray code, excess-3 code, etc Simple code conversion process is done with the help of combinational Truth table having the conversion from BCD code to gray code Gray code (Output) Decimal ee G | Ge | Gi | Go eo felelel[olelo|lolfe 1 [elele{[:[el[e|leo]a 2 [ele|s}elefe|ala 3 [efels|[s:]elelale 4 _[elslelele|: ala o felsfel{s[els]+|[s 6 felsts{elelale|[a KS ESESEe eo 8 [slelel[eol[s[:]lele 9 lelfelel[=|:]:][els [email protected] 29“ Binary to/from Gray Cod : : Decimal K map: GO K map: Gi eee alediede b bs. ~—————_——-. 9 o felefefofoleo|lol|o + lelelo[:s[felele|: 2 fele{s|eleleo]s {a b p> ge seater [ao | eo a7 4 ° 1 ° ° ° 1 1 ol eo felzfe{:fe,s|a]a 6 ° x a ° ° 1 ° 1 91 7 [els]s[:]/el[:[ele bi @ [s}efoleo{z]a]feo]o 29 l:fefel:]:]:]e]|2 bal Corresponding minimized Boolean expressions for gray code bits 90 = by) + Dib, = by B by I = byl, + by, = by S by 92 = bab, + bab = by © by 93 = bs 7 November 2022 [email protected] 30 bo So .Dr. CARUNAISELVANE.C Assistant Professor Automobile Engineering Department SRM Institute of Science and Technology. edu.in carunaic@srmi +91 8265804594 cholar google. com/ei 2userImvi Ke ttns://www researcheate neU/profile/Carunaiselvane_Carounagarane https://www, linkedin. com/in/dr-carunaiselvane-c-88b41723/ ng College, Pon | Pondicherry Engineer je has receiv carunaiselvane Carounagarane (5/16) received the 8.Tech and the M.Tech. degree in electrical drive and control from dia, in 2008 and 2012, respe ogy Roorkee, India in 2020 u he is currently