Digital Logic Design

Chapter V
Combinational logic
Addis Ababa Science and Technology University
College of Electrical and Mechanical Engineering
Department of SE
Lecturer: Biruk T.
1
Introduction
• Logic circuit for digital systems maybe combinational or sequential.
• A combinational circuit consists of logic gates whose outputs at
any time are determined from only the present combination of inputs.
• A combinational circuit performs an operation that can be specified
logically by a set of Boolean functions.
• In contrast, sequential circuits employ storage elements in addition
to logic gates.
• The outputs of sequential circuits are a function of the input and the
state of the storage elements.

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Basic Combinational Logic Circuits
• AND-OR logic circuit
➢ Directly implements an SOP expression.
• AND-OR-Inverter logic circuit
➢ This kind of implementation leads to POS expression.
• Exclusive-OR logic circuit
➢ A combination of two AND gates, one OR gate and two inverters.
• Exclusive-NOR logic circuit
➢ Implemented by simply inverting the output of an exclusive-OR.

3
Exclusive-OR Implementations
◼ Implementations
❑ (x'+y')x + (x'+y')y = xy'+x'y = xy

Exclusive-OR Implementations

4
Functions of combinational logic circuit

• A combinational circuit consists of an interconnection of logic gates.

• For n inputs variables, there are 2n possible combination of the binary

inputs. For each possible input combination, there is one possible
value for each output variable.

• A combinational circuit also can be described by m Boolean functions,

one for each output variable. Each output function is expressed in
terms of the n output variables.

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DESIGN PROCEDURE
• The design of combinational circuits starts from the specification of
the design objectives and is converted to a set of Boolean functions
from which the logic diagram can be obtained.
• The procedure involves the following steps;
1. Understand the full operation
2. Determine the required number of inputs and outputs and assign a symbol
to each.
3. Derive the truth table that defines the required relationship between inputs
and outputs.
4. Obtain the simplified Boolean functions for each output as a function of the
input variables.
5. Draw the logic diagram and verify the correctness of the design.

6
BASIC ADDERS (Arithmetic Binary Adder)

• Adders are important in computers and also in other types of digital

systems in which numerical data are processed.
• An understanding of the basic adder operation is fundamental to the
study of digital systems.
• The Half-Adder
➢
.

➢ The operations are performed by a logic circuit called a half-adder

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BASIC ADDERS (Arithmetic Binary Adder)

• The half-adder accepts two binary digits on its inputs and produces
two binary digits on its output, a sum bit and a carry bit.

• Expressions can be derived for the sum and the output carry as
functions of the inputs. Notice that the output carry is a 1 only when
both A and B are 1. so Cout = AB
8
• This circuit needs two binary inputs and two binary
outputs. The input variables designate the augend and
addend bits; the output variables produce the sum and
carry.

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BASIC ADDERS (Arithmetic Binary Adder)
• Observe that the sum output is a 1 only if the input variables A and B
are not equal. The sum can therefore be expressed as the XOR of the
input variables.

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BASIC ADDERS (Arithmetic Binary Adder)
• The Full-Adder
• The second category of adder is the full-adder
• The full-adder accepts two inputs bits and an input carry and generates a sum
output and an output carry. The basic difference between a full-adder and a
half-adder is that the full-adder accepts an input carry.

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BASIC ADDERS (Arithmetic Binary Adder)
• The full adder must add the two inputs bits and the input carry.
• From the half-adder you know that the sum of the inputs bits A and B
is the XOR of those two variables.
• For the input carry to be added to the input bits, it must be XORed
with
• For the input carry (Cin) to be added to the input bits, it must be
XORed with . This means that to implement the full-adder sum
function , the 2-input XOR gate can be used.

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BASIC ADDERS (Arithmetic Binary Adder)

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Parallel Binary Adders
• Two or more full-adders are connected to form parallel binary adders.
• To add two binary numbers, a full-adder is required for each bit in the
numbers. So,
• For 2-bit numbers, two adders are needed
• For 4-bit numbers, four adders are used and so on

• The carry output of each adder is connected to the carry input of the
next higher-order adder.

16
2-bit Numbers

17
4-bit Parallel Adders
• A group of four bits a called nibbles.

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20
Magnitude Comparators
• The basic function of a comparator is to compare the magnitude of
two binary quantities to determine the relationship of those
quantities.
• Example 2-bit comparator;

• In order to compare binary numbers containing two bits each, an

additional XOR gate is necessary
21
Logic diagram for equality comparison of two 2-bit numbers

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23
Decoders
• A decoder is digital circuit that detects the presence of a specified combination of
bits (code) on its inputs and indicates the presence of that code by a specified
output level.
• In its general form, a decoder has n inputs lines to handle n bits and from 1 to 2n
output lines to indicate the presence of one or more n- bit combinations.
• Decoder can be developed using AND logic gates.

• The basic principles can be extended to other types of decoders.

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Decoders
▪ Extract “Information” from the code Only one lamp
will turn on
▪ Binary Decoder
• Example: 2-bit Binary Number

1
0
x1
0
Binary
0 Decoder 0
x0
0

Boolean Algebra and Logic Gates 25

Decoder
• Black box with n inputs lines and 2𝑛 output lines.
• Only one output is a 1 for any given input.

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2-to-4 Binary Decoder

• A certain application requires that a 5-bit number be decoded. Use 74HC154 decoders
to implement the logic. The binary number is represented by the format A4A3A2A1A0.
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Since the 74HC154 can handle only four bits, two decoders must be used to form a
5-bit expansion. The fifth bit, A4, is connected to the chip select inputs, CS1 and CS2,
of one decoder, and A4 is connected to the CS1 and CS2 inputs of the other decoder, as shown
in Figure .
When the decimal number is 15 or less, A4 = 0, the low-order decoder is enabled, and the
high-order decoder is disabled. When the decimal number is greater than 15, A4 = 1 so A4 =
0, the high-order decoder is enabled, and the low order decoder is disabled.

Individual Assignments 1
Design a decoder for 3 binary input

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Decoder with an enable input
• Decoders include one or more enable inputs to control the circuit
operation.

31
4-to-16 line decoder (using two 3-to-8 decoder)
• In order to decoder all possible combination of four bits, 16th
decoding gates are required.
• Decoders with enable inputs can be connected together to form a
larger decoder circuit.

32
BCD-to-7-Segment Decoder/Driver
The BCD-to-7-segment decoder accepts the BCD code on
its inputs and provides outputs to drive 7-segment display
devices to produce a decimal readout.

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Decoder - Applications
• The BCD-to-7-Segement Decoder

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Decoder - Applications

• The BCD-to-Decimal
Decoder
• 4-line-to-10-line decoder

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Individual Assignments X

Design a binary(4) to HEX Decoder

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Encoder
• An encoder accepts an active level on one of its inputs representing a
digit, such as a decimal or octal digit, and converts it to a coded
output, such as BCD or binary.
• The process of converting from familiar symbols or numbers to a
coded format is called encoding.

• Put “Information” into code

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Encoders I7
I6
• Octal-to-Binary Encoder (8-to-3) I5

Encoder
Y2

Binary
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I4 Y1
0 0 0 0 0 0 0 1 0 0 0 I3 Y0
0 0 0 0 0 0 1 0 0 0 1 I2
0 0 0 0 0 1 0 0 0 1 0 I1
0 0 0 0 1 0 0 0 0 1 1 I0
0 0 0 1 0 0 0 0 1 0 0 I7
0 0 1 0 0 0 0 0 1 0 1 I6 Y2
0 1 0 0 0 0 0 0 1 1 0 I5
1 0 0 0 0 0 0 0 1 1 1 I4
I3 Y1
Y2 = I 7 + I 6 + I 5 + I 4 I2
I1
Y1 = I 7 + I 6 + I 3 + I 2 I0 Y0
Y0 = I 7 + I 5Powerpoint
+ I 3 + I1 Templates Page 39
Encoder - Application

• The Decimal-to-BCD Encoder

• This is a basic 10-line-to-4-line encoder

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Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2 Y4
I4 Y1 I1 Y3
I3 Y0 I0 Y2
I2
I1 Y1
I0 Y0

Powerpoint Templates
Page 41
Individual Assignments 2
Design a HEX to BCD Encoder

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Multiplexers (Data Selectors)
• A multiplexer (MUX) is a device that allows digital information from
several sources to be routed onto a single line for transmission over that
lines to a common destination.
• The basics multiplexer has several data-input lines and a single output line.
• It has data-select inputs, which permit digital data on any one of the inputs
to be switched to the output line.

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Multiplexers (Data Selectors)

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Multiplexers
• 2-to-1 MUX
I0
I0 Y
I1 MUX Y I1
S
S

• 4-to-1 MUX I0

I1
Y
I0 I2

I1 I3
MUX Y
I2
I3
S1 S0
Powerpoint Templates S1 S0
Page 45
Multiplexers
• Quad 2-to-1 MUX A3
Y3
A2
x3 I0 Y2
y3 MUX Y A1
I1 Y1
S
A0
Y0
x2 I0 B3
y2 MUX Y
I1
S B2
A3
B1 A2
x1 I0 A1
Y3
y1 MUX Y B0 A0
I1 Y
MUX Y2
S 1
B3 Y0
B2
x0 I0 S E
B1
y0 MUX Y
I1 B0
S S E

S
Powerpoint Templates
Page 46
Implementation Using Multiplexers
• Example
F(x, y) = ∑(0, 1, 3)
x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

Powerpoint Templates
Page 47
Multiplexer Expansion
• 8-to-1 MUX using Dual 4-to-1 MUX
I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
I1 MUX Y Y
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0

1 Powerpoint
0 0 Templates
S2 S1 S0 Page 48
Multiplexer

Assignment :- Construct a 16  1 multiplexer with two 8  1 and one 2  1

multiplexers. Use block diagrams.
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Demultiplexers (Data Distributor)
• A demultiplexer (DEMUX) basically reverse the multiplexing function.
• It takes digital information form one line and distributes it to a given number of output
lines.
• Data goes from one line to several lines.

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Demultiplexer

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DeMultiplexers
Y3
Y2
I DeMUX
Y1
S S Y0
1 0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
Powerpoint Templates
Page 52
Multiplexer / DeMultiplexer Pairs
MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y I Y3
I3
I2 Y2
I1 Y1
I0 Y0

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
Powerpoint Templates
Page 53
DeMultiplexers / Decoders
Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX I0 Y1
Y1
E Y0
S S Y0
1 0

E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0
Powerpoint Templates
Page 54
End of Chapter V
Questions?

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