.

3.8 INTERRUPTS
Microprocessor fetches the instruction codes from memory in sequence and executes. The
microprocessor may be int_errupted in the middle of a program to handle some emerge~cy
tasks. The origin for the interrupt may be internal or external to the microprocessor. · , -- ·
When an interrupt occurs in response to the microprocessor completes the execution of
current instruction in the program, jumps to a subroutine program called interrupt service
procedure, and executes the ins~ctions in the interrupt service procedure. After~ interrupt
service procedure is completed, the execution returns back to the interrupted program and
continues.

3.8.1 Interrupt Vector Table

The microprocessor reserves the first 1,024 bytes of, memory, from 0000:0000H to
0000:03FFH, to hold the starting addresses of intef11:Ipt service procedures. The starting
address of an 'i nterrupt service procedure is called as interrupt vector and. the first 1,024 bytes
of memory is called as interrupt vecto~ table. This is illustrated here in Figure 3.36. {)be
interrupt vector table can hold up to 256 interrupt vectors. Each vector is saved in CS:IP format
in four consecutive bytes in memory and the vector identified by a type number o through 25S..
Vector for type O is stored in locations , 0000:0000H-0000:0003H, vector for_type 1-is stored
in locations 0000:0004H-0000:0007H and _s o on. Figure 3.36 shows the interrupt vector table.
0000 : 0400 .,

:rype - 25
0000 : 03F8

:Y-ype - 25
0000 : 03F4
I·
:rype - 253
0000 : 03F0
~
(

Type - 8
0000 : 0020

Type- 7 ' .
0000: 00IC

Type- 6
0000 : 0018

Type - 5
0000 : 0014

Type-4 .'
0000 : 0010
/
Type~-3
~ . • •: I
0000: oooc

Type-2
cs ·,
IP "
0000 : 0008

Type - 1
IP
0000 : 0004

Type- O
cs
. IP . '
.' .
0000 : 0000

Figure 3.36 Interrupt vector table.

·'
.. ' 4
3.8.2 The 8086 Response to Interrupts
At the end of each instruction cycle, the microprocessor checks if any interrupt is active. Wh;
the processor detects active interrupt, the following sequence of events occurs:
(a) The content of the flag register is pushed into the stack.
(b) The interrupt flag (IF) is cleared to disable interrupt through INTR input.
(c) The trap flag (TF) is reset to disable single step function.
(d) . of CS and IP registers are pushed into stack.
Contents .
(e) Interrupt vector of the interrupt service procedure is obtained from the interrupt
vector table and CS and IP registers are filled.
( f) Interrupt service procedure is eX:ecuted.
(g) The last instruction in the interrupt service procedure will be IRET and when the
instruction is executed, · I '
·
(i) ~etum address, pushed into the stack in step (d), ·is poped back into CS and IP
registers; :
(iI) The status of flags, pushed into the stack in step (a), is poped back into the flag
register.
(h) Execution returns to the interrupted program
..,, .
;

The response of microproce.ssor to interrupts is sc~ematically illustrated in Figure 3.38.

3.8.3 8086 Interrupt Types

The 8086 interrupts are classified into three types. They are:
• Predefined interrupts . ,. .
• Software interrupts
• Hardware interrupts

Predefined interr~pts
InterrUPt types O ~ugh 31 have been defined as predefined inte~~ts and only· the interrupt
. Interrupt
Service
Main Line
Program Procedure
PUSH FLAGS, CLEAR IF,

1-
TF PUSH CS, IP
(Save return address) PUSH
Get ISP address from Registers
interrupt vector table
Interrupt
recognized

Returns
from
interrupt POP IP, CS
(Get return address) POP~--,
FLAGS from STACK
• I

POP
Registers
'-----4 IRET

Figure 3.38 . Respo~se of 8086 to, , interrupts.

r - f .
types O through 4 are used in 8086. . Interrupt types,, 5 t~rough 31 ar~ reserved for use in
advanced versions. The predefined interrupts are divide PY . zero, single step,_ non-maskab le,
breakpoint, and overflow ~t~n:upts. · ~ · · · , .',; :- , , ·

Divide by zero interrupt, Iype 0. . The divide by zero interrupt occurs whenever a division by
zero is attempted using a divide instruction. When the interrupt ·occurs~ the microproce ssor
automatically perfonns type O interrupt respo~se, This interrupt is nori-maskab le.
Single step interrupt, Iype 1. The single step interrupt occurs after the execution of ,.,
an instruction, if the trap flag {TF) in the program status word (PSW) is set. When the
interrupt oc<;urs, . the .microproces sor automaticall y performs type 1 interrupt response. The
interrupt service procedure for the single step_in!errupt_usually provides various diagnostic
capabilities · · . ·. . , · . ·
• r · • • I ,.
1
• • ~ •

· The single step · interrupt is used to exe~ute the program one instruction at a time. When
the execution enters the interrupt service procedure, it saves PSW . in the. stack. When the
execution leaves the. procedure by executing IRET instruction, it restores the PSW from the
stack (including the TF, which continues to remain set). It allows another single step interrupt
t~ occur after the next instruction is execut~d.. Hence, the execution continues to progress in
Slll~e step. . '. . . . ·
Tb.ere is no· direct instructioh to set or reset the TF. The simpl_e program in Listin 3
.sets and resets the TF indirectly. · · g ·4
If
Non-m askab le inten-upt (NM/), 7ype· i. .
The ~on-maskable in .
high transi tion is applie d on NMI. input pin of the micro proce
micro proce ssor ·autom aticall y perfor ms type 2 interru pt respoqse. ··
disabl ed or maske d by any instruction.- It is generally use~ to skve- · ·
to non-v olatile region in memory when power to the system ·
. . . . .

Break point interrupt, · 'lj,pe 3. The break

.
point interru t ·
~

instruc tion, INT3. The instruction is inserted in a program w

It is useful for progra m debugging. The interrupt is n · ~
&£.I

Overflow interry,pt, Type 4. The overflow interrup occurs

set as a result of an arithm rtic operation on two
sign
instruc tion (INTO ) is executed. The microprocessor
I

i:esponse when the interrupt occurs . For the 'interrup

immed iately follow the arithmetic instructio~ If the ·
operat ion, the next INTO instruction simply performs
non-m askabl e.
Softw are interr upts
The micro proces sor may be interru pted when it 'execu ~~•11
~;~te
. instruc tion in the program. It is referred to as ·software m".......,,_
·specif ies th~ interrupt type and talces a value betwe en O and 2S
the ~crop rocess or gets the inte~ pt vecto~ for th~ type·'n'
interrupt service procedure. ·· , . . -' . ·
· Bas~c Input and Ou~u~ Service~ (BIOS) interrupts in -~ p
software mte~ pts. BIOS 1s a collection of se~ice routines that
· control hardware components of a PC. Routines controlling the video
and mouse of the PC are called by software interrupt · tru .
17H, and INT 33H respectively. ms cttons

Hardware inter,;upts
The ntlcroprocessor has two interrupt inputs. They ar N ·
Interru pt Reque st (INTR). The processor may be . t e on-Ma skable Interrup
signal applied to one of the_two interrupt inputs. in errupted by an external as
NMI
Whenever the NMI input is activated (a low to high transition), a type 2 interrupt t1ccurs and
the microprocessor automatically performs type 2 response.
A common application for the NMI input is to save critical data in the event of power
failure. A circuit detecting power failure sends interrupt signal to the NMI input. Usually the
capacitors in the system power supply can provide de voltage for a minimum period of
50 ms even after the power failure. This period is enough for the microprocessor to perfonri
type 2 response, which moves critical data from RAM to memory with battery backup.

Example 3.9
Give an application for NMI interrupt.
Solution , . . ,
. t
NMI interrupt is used to get the immediate attention of microprocessor to perform emergency
operations. Interrupt through NMI input is demonstrated by connecting a smoke detector to the
microprocessor.
Smoke detect~rs are used in industries to ~onitor industrial safety. When the smoke
detector detects smoke, it generates an interrupt pulse and sends to NMI input. Since the NMI ·
interrupt is non-maskable and has top most priority, the microprocessor immediately attends to
the request and performs type 2 interrupt response. The interrupt service procedure will have
instructions to send control word to switch OFF the process causing the smoke. Figure 3.39
illustrates the technique. The interrupt service procedure for handling the NMI interrupt is given
in Listing 3.5.

Micro-
processor

Smoke
detecting NMI
syste"'.l

I I

./ igure 3.39 NMI interrupt.

INTR .,
External devices requiring the immediate attention of the microprocessor intem1pt through the
interrupt request (INTR) input. Logic high to INTR pin activates the intenupl When the
interrupt is activated, the 8086 gets the interrupt type from an external device such as a priority
interrupt controller, 8259A and perfonns the intenupt response. This interrupt is useful in
interfacing slow devices to microprocessors. It is level-sensitive and can be enabled or d ~
by setting or resetting' the interrupt flag (IF) bit of the PSW. The IF bit of the PSW is set !,y
'S!1' instruction and ·reset by 'CLI' instruction:' . · - ·

Handling INTR interrupt. The response of 8086 to lNTR interrupt is somewhat different
from other intenupts. For the other intenupts, the 8086 automatically performs a Imo
response. But, for the interrupt through INTR, the 8086 gets the interrupt type from an ex
device such as a priority interrupt controller, 8259A and performs the interrupt response.
is shown in Figure 3.40. ~ . · ,· ;

--+-~..---------
Address Bus - - . - -......~ - - - - -

Data Bus

_ __. DO R> ~ - .!
8086 D1 IR1 i
---'02 · , A2 C
---103 I R3 -
'S.
_ __.! .-
D4 IR4~-
n;IR7IR5 i
c
INTA INTA -
MR ~--------J NT
8259A
cs
I
I
/
· Figure_3.40 INTR interrupt.
..
The 8259A-ca • dev·
n receive interrupt.signal from One of eight
• IR7 and tees conn
intenupt request mputs. IR0 through. pass onto the mic
. . . roprocessor
the mtenupt IS 2cogmzed, the microprocessor performs
(sends two INTA pulses). In the first, it prepares th 8259 two mterrupt-acknowled
the interrupt In the second, it receives the type fro ~259 to ge~ ready to send
the respective intenupt resp(!nse. The advantage 0 f m. · The microprocessor then
usmg an external device to provide di
3.8.4 Prio rity of 808 6 Inte rrup ts .
' ~

than one inter rupt occu rs at a tune.

.

The 8086 assig ns prior ity amon g vario us inter rupts , if more
have high est prior ity amo ng
The divide by zero and the softw are instructions INT n and INTO
-a11 interrupts. NMI , INT R and singl e-ste p interrupts have prior
ities µi the decr easin g orde r. It
le-st ep inter rupts caus e the
pleans that simu ltane ous divid e by zero and NMI /INT /sing
the othe r inter rupt. Simi larly ,
microprocessor to serve divid e by zero inter rupt first, follo wed by
r to exec ute type · 2 resp onse
simultaneous NMI and INTR interrupts caus e the micr opro cesso
~ first and INTR inter rupt type next.. The singl
e-ste p interrupt- has the least prior ity.
.

3.9 ·»IR EC T ME MR OY AC CE SS
s to trans fer a data from an
Microprocessor perfo rms 1/0 read and mem ory write oper ation
1/0 device to a mem ory. Similarly, it perfo rms a mem ory read
and an 1/0 -writ e oper ation s to
betw een a mem ory and an
transfer a data from mem ory to 1/0 device. Ever y data trans fer
ory acce ss (OM A) tech niqu e
· 1/0 device goes throu gh the micr opro cesso r. The direc t mem
les fast and bulk data trans fer
provides direc r acce ss betw een mem ory and 1/0 devi ce and enab
· ·
without the assis tance of a micr opro cesso r.

3.9.1 Bas ic DM A Ope rati on

A (OM A ackn owle dge)
The 8086 in mini mum mod e h~ HOL D (DM A requ est) inpu t and HLD
the basic DM A oper ation . A
ou~u t pins to supp ort OMA oper ation . Figu re 3.42 illus trate s
DMA oper ation .
de~ice calle d DAM cont rolle r such as 8237 cont rols the comp lete
d as DMA write and data
DMA. cont rolle d data trans fer from 1/0 devi ce to mem ory is calle
transfer from mem ory to 1/0 devi ce is calle d as DMA real An 1/0
devi ce, requ estin g the DM A
in tum, the OM A cont rolle r
· read or Write oper ation , send s DRE Q to the OMA contr oller , and
micr opro cesso r. sam ples th
~ends h?ld requ est HRQ to the micr opro cesso r HOL D µipu t. The
opro cess or dete cts the HOL ~
si OLD _lllput in the midd le of ev~ clo~ k cycle . ~en the micr
o:a1, 1t stops exec uting furth er mstr uctio ns, float s its buse s and send
DA) signa l to the DMA controller. The DMA cont rolle r then send s
s out hold acknowled
out a cont rol sign al:
ALE 1

f
Address -~ - -
--
Micro- Address Bus
processor '""
Data
- .,
I

Control I
HOLD
HLDA
-
.J
- ~
-
Data Bus
-- Memory

j ' ' .

1 I - Control Bus - .
t-RQ HLDA .J
-
Address
;

.
j ' j '

OMA Control . .t ,~
I-'-'
Controller ,
AEN ...\ - -
... ,
-
-
.' -: .
I--

ADSTB Peripheral
a:EQ -
r 1•
..• ...
'·
.. - , .: .
' 'l ·, --
. .
DACK , , ,. ·,
, '
' ' ., -'
Figu;e 3.42 Basic , OMA operation.
' '
I ,: ' )

virtually disconnect the microprocessor from the a~dress, data and control buses, and connec
the OMA controller. 'J1le DMA controller thus gets the control of the buses and sends out th
memory address on the address bus where the first byte of data from or to the. 1/0 device
to be transferredtThen, it sends DMA acknowled~e (DACK) signal to ll?,e I/0 device. Finall
it sends ou.!._!!!.emory read ( ME~R ) and 1/0 wnte ( IOW ) control signals for OMA read
1/0 read ( IOR) and memory wnt~ ( MEMW) control signals for DMA write · the con on
bus. It enables the byte. of data directly to go between the 1/0 device and memory with
passing through the microp!ocessor o~ the DMA controller.· · . . · • · .
After the data transfer 1s complete, the DMA controller disables HOLD signal and rele
the control of address, data and control buses back to the microprocessor, by virtu
disconnecting the buses from the DMA controller and connecting
i; : . #. t
mforoprocessot to the
. I