+

William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 12
Instruction Sets:
Characteristics and Functions
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+
Machine Instruction
Characteristics

 The operation of the processor is determined by the

instructions it executes, referred to as machine instructions or
computer instructions

 The collection of different instructions that the processor can

execute is referred to as the processor’s instruction set

 Each instruction must contain the information required by the

processor for execution

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Elements of a Machine Instruction

Operation code Source operand

(opcode) reference
• Specifies the operation • The operation may
to be performed. The involve one or more
operation is specified source operands, that
by a binary code, is, operands that are
known as the operation inputs for the operation
code, or opcode

Result operand Next instruction

reference reference
• The operation may • This tells the processor
produce a result where to fetch the next
instruction after the
execution of this
instruction is complete

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Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand

Data
address operation address address
Operation
calculation decoding calculation calculation

Return for string

Instruction complete, or vector data
fetch next instruction

Figure 12.1 Instruction Cycle State Diagram

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Source and result operands can be
in one of four areas:
3) Processor register
 A processor contains one or
1) Main or virtual memory more registers that may be
 As with next instruction referenced by machine
references, the main or virtual instructions.
memory address must be
supplied  If more than one register
exists each register is
assigned a unique name or
number and the instruction
2) I/O device must contain the number of
 The instruction must specify the desired register
the I/O module and device for 4) Immediate
the operation. If memory-
mapped I/O is used, this is  The value of the operand is
just another main or virtual contained in a field in the
memory address instruction being executed

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+
Instruction Representation
 Within the computer each instruction is represented by a
sequence of bits

 The instruction is divided into fields, corresponding to the

constituent elements of the instruction
4 bits 6 bits 6 bits

Opcode Operand Reference Operand Reference

16 bits

Figure 10.2 A Simple Instruction Format

Figure 12.2 A Simple Instruction Format

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+
Instruction Representation
 Opcodes are represented by abbreviations
called mnemonics

 Examples include:
 ADD Add
 SUB Subtract
 MUL Multiply
 DIV Divide
 LOAD Load data from memory
 STOR Store data to memory

 Operands are also represented symbolically

 Each symbolic opcode has a fixed binary representation

 The programmer specifies the location of each symbolic operand

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Instruction Types
• Arithmetic instructions provide • Movement of data into or
computational capabilities for out of register and or
processing numeric data memory locations
• Logic (Boolean) instructions operate
on the bits of a word as bits rather
than as numbers, thus they provide
capabilities for processing any
other type of data the user may wish
to employ

Data Data
processing storage

Data
Control
movement
• Test instructions are used to test the • I/O instructions are needed
value of a data word or the status of a to transfer programs and
computation data into memory and the
• Branch instructions are used to branch results of computations
to a different set of instructions back out to the user
depending on the decision made

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Instruction Comment
SUB Y, A, B Y¬A–B
MPY T, D, E T¬D´E
ADD T, T, C T¬T+C
DIV Y, Y, T Y¬Y÷T

Instruction Comment
(a) Three-address instructions
LOAD D AC ¬ D
MPY E AC ¬ AC ´ E
Instruction Comment ADD C AC ¬ AC + C
MOVE Y, A Y¬A STOR Y Y ¬ AC
SUB Y, B Y¬Y–B LOAD A AC ¬ A
MOVE T, D T¬D SUB B AC ¬ AC – B
MPY T, E T¬T´E DIV Y AC ¬ AC ÷ Y
ADD T, C T¬T+C STOR Y Y ¬ AC
DIV Y, T Y¬Y÷T

(b) Two-address instructions (c) One-address instructions

A- B
Figure 12.3 Programs to Execute Y=
C+ (D´ E)
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Table 12.1
Utilization of Instruction Addresses
(Nonbranching Instructions)

Number of Addresses Symbolic Representation Interpretation

3 OP A, B, C A ¬ B OP C
2 OP A, B A ¬ A OP B
1 OP A AC ¬ AC OP A
0 OP T ¬ (T – 1) OP T

AC = accumulator
T = top of stack
(T – 1) = second element of stack
A, B, C = memory or register locations

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Instruction Set Design
Very complex because it affects so many aspects of the computer system

Defines many of the functions performed by the processor

Programmer’s means of controlling the processor

Fundamental design issues:

Operation repertoire Data types Instruction format Registers Addressing

• How many and which • The various types of data • Instruction length in bits, • Number of processor • The mode or modes by
operations to provide and upon which operations are number of addresses, size registers that can be which the address of an
how complex operations performed of various fields, etc. referenced by instructions operand is specified
should be and their use

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Types of Operands

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+ Numbers

 All machine languages include numeric data types

 Numbers stored in a computer are limited:

 Limit to the magnitude of numbers representable on a machine
 In the case of floating-point numbers, a limit to their precision

 Three types of numerical data are common in computers:

 Binary integer or binary fixed point
 Binary floating point
 Decimal

 Packed decimal
 Each decimal digit is represented by a 4-bit code with two digits
stored per byte
 To form numbers 4-bit codes are strung together, usually in multiples
of 8 bits

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+
Characters

 A common form of data is text or character strings

 Textual data in character form cannot be easily stored or

transmitted by data processing and communications systems
because they are designed for binary data

 Most commonly used character code is the International

Reference Alphabet (IRA)
 Referred to in the United States as the American Standard Code
for Information Interchange (ASCII)

 Another code used to encode characters is the Extended

Binary Coded Decimal Interchange Code (EBCDIC)
 EBCDIC is used on IBM mainframes

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+
Logical Data

 An n-bit unit consisting of n 1-bit items of data, each item

having the value 0 or 1

 Two advantages to bit-oriented view:

 Memory can be used most efficiently for storing an array of
Boolean or binary data items in which each item can take on only
the values 1 (true) and 0 (false)
 To manipulate the bits of a data item
 If floating-point operations are implemented in software, we
need to be able to shift significant bits in some operations
 To convert from IRA to packed decimal, we need to extract the
rightmost 4 bits of each byte

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Data Type Description
General Byte, word (16 bits), doubleword (32 bits), quadword (64 bits),
and double quadword (128 bits) locations with arbitrary binary
contents.
Integer A signed binary value co4ntained in a byte, word, or doubleword,
using twos complement representation.
Ordinal An unsigned integer contained in a byte, word, or doubleword.
Unpacked binary coded
decimal (BCD)
A representation of a BCD digit in the range 0 through 9, with one
digit in each byte. Table 12.2
Packed BCD Packed byte representation of two BCD digits; value in the range 0
to 99.

x86
Near pointer A 16-bit, 32-bit, or 64-bit effective address that represents the
offset within a segment. Used for all pointers in a nonsegmented
memory and for references within a segment in a segmented

Data Types
memory.
Far pointer A logical address consisting of a 16-bit segment selector and an
offset of 16, 32, or 64 bi ts. Far pointers are used for memory
references in a segmented memory model where the identity of a
segment being accessed must be specified explicitly.
Bit field A contiguous sequence of bits in which the position of each bit is
considered as an independent unit. A bit string can begin at any bit
position of any byte and can contain up to 32 bits.
Bit string A contiguous sequence of bits, containing from zero to 232 – 1
bits.
Byte string A contiguous sequence of bytes, words, or doublewords,
containing from zero to 232 – 1 bytes.
Floating point See Figure 12.4.
Packed SIMD (single Packed 64-bit and 128-bit data types
instruction, multiple data)

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Byte unsigned integer
7 0

Word unsigned integer

15 0

Doubleword unsigned integer

31 0

Quadword unsigned integer

63 0
sign bit
twos comp
Byte signed integer
7 0
(twos complement)
sign bit
Word signed integer
15 0
(twos complement)
sign bit
Doubleword signed integer
31 0
(twos complement)
sign bit
Quadward usigned integer
63 0
(twos complement)t
sign bit
exp signif.
Half precision
15 9 0
floating point
sign bit
exp significand
Single precision
31 22 0
floating point
sign bit
exp significand
Double precision
63 51 0
floating point

sign bit integer bit

exponent significand
Double extended precision
floating point
79 63 0

Figure 12.4 x86 Numeric Data Formats

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+
Single-Instruction-Multiple-Data
(SIMD) Data Types

 Introduced to the x86 architecture as part of the extensions of the

instruction set to optimize performance of multimedia applications

 These extensions include MMX (multimedia extensions) and SSE

(streaming SIMD extensions)

 Data types:
 Packed byte and packed byte integer
 Packed word and packed word integer
 Packed doubleword and packed doubleword integer
 Packed quadword and packed quadword integer
 Packed single-precision floating-point and packed double-precision
floating-point

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ARM Data Types
ARM processors support
data types of:
•8 (byte)
•16 (halfword)
•32 (word) bits in length

All three data types can Alignment checking

also be used for twos •When the appropriate control
complement signed bit is set, a data abort signal
indicates an alignment fault for
integers attempting unaligned access

For all three data types Unaligned access

an unsigned
interpretation is •When this option is enabled,
the processor uses one or
supported in which the more memory accesses to
value represents an generate the required transfer
unsigned, nonnegative of adjacent bytes transparently
to the programmer
integer
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Data bytes
in memory
(ascending address values
from byte 0 to byte 3)
Byte 3

Byte 2

Byte 1

Byte 0

31 0 31 0
Byte 3 Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2 Byte 3

ARM register ARM register

program status register E-bit = 0 program status register E-bit = 1

Figure 12.5 ARM Endian Support - Word Load/Store with E-bit

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Type Operation Name Description
Move (transfer) Transfer word or block from source to destination
Store Transfer word from processor to memory
Load (fetch) Transfer word from memory to processor
Exchange Swap contents of source and destination
Data Transfer
Clear (reset) Transfer word of 0s to destination

Table 12.3
Set Transfer word of 1s to destination
Push Transfer word from source to top of stack
Pop Transfer word from top of stack to destination
Add Compute sum of two operands

Common
Subtract Compute difference of two operands
Multiply Compute product of two operands

Arithmetic
Divide
Absolute
Compute quotient of two operands
Replace operand by its absolute value
Instruction Set
Negate
Increment
Change sign of operand
Add 1 to operand
Operations
Decrement
AND
Subtract 1 from operand
Perform logical AND
(page 1 of 2)
OR Perform logical OR
NOT (complement) Perform logical NOT
Exclusive-OR Perform logical XOR
Test Test specified condition; set flag(s) based on outcome
Logical
Compare Make logical or arithmetic comparison of two or more
operands; set flag(s) based on outcome
Set Control Class of instructions to set controls for protection
Variables purposes, interrupt handling, timer control, etc.
Shift Left (right) shift operand, introducing constants at end (Table can be found on page
Rotate Left (right) shift operand, with wraparound end 426 in textbook.)
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Type Operation Name Description
Jump (branch) Unconditional transfer; load PC with specified address
Jump Conditional Test specified condition; either load PC with specified
address or do nothing, based on condition
Jump to Subroutine Place current program control information in known
location; jump to specified address

Table 12.3
Return Replace contents of PC and other register from known
location
Execute Fetch operand from specified location and execute as
Transfer of Control instruction; do not modify PC
Skip Increment PC to skip next instruction
Skip Conditional Test specified condition; either skip or do nothing based
on condition Common
Halt
Wait (hold)
Stop program execution
Stop program execution; test specified condition
Instruction Set
No operation
repeatedly; resume execution when condition is satisfied
No operation is performed, but program execution is Operations
(page 2 of 2)
continued
Input (read) Transfer data from specified I/O port or device to
destination (e.g., main memory or processor register)
Output (write) Transfer data from specified source to I/O port or device
Input/Output Start I/O Transfer instructions to I/O processor to initiate I/O
operation
Test I/O Transfer status information from I/O system to specified
destination
Translate Translate values in a section of memory based on a table
of correspondences
Conversion
Convert Convert the contents of a word from one form to another (Table can be found on page
(e.g., packed decimal to binary) 426 in textbook.)

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Table 12.4
Processor Actions for Various Types of Operations
Transfer data from one location to another
If memory is involved:
Data Transfer Determine memory address
Perform virtual-to-actual-memory address transformation
Check cache
Initiate memory read/write
May involve data transfer, before and/or after
Arithmetic Perform function in ALU
Set condition codes and flags
Logical Same as arithmetic

Conversion Similar to arithmetic and logical. May involve special logic to

perform conversion
Update program counter. For subroutine call/return, manage
Transfer of Control
parameter passing and linkage
Issue command to I/O module
I/O
If memory-mapped I/O, determine memory-mapped address

(Table can be found on page 427 in textbook.)

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Data Transfer

Must specify:
• Location of the source and
destination operands
Most fundamental type of • The length of data to be
machine instruction transferred must be indicated
• The mode of addressing for each
operand must be specified

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Table 12.5
Examples of IBM EAS/390 Data Transfer Operations
Operation Number of Bits
Mnemonic Name Transferred Description
L Load 32 Transfer from memory to register
LH Load Halfword 16 Transfer from memory to register
LR Load 32 Transfer from register to register
LER Load (Short) 32 Transfer from floating-point register to
floating-point register
LE Load (Short) 32 Transfer from memory to floating-point
register
LDR Load (Long) 64 Transfer from floating-point register to
floating-point register
LD Load (Long) 64 Transfer from memory to floating-point
register
ST Store 32 Transfer from register to memory
STH Store Halfword 16 Transfer from register to memory
STC Store Character 8 Transfer from register to memory
STE Store (Short) 32 Transfer from floating-point register to
memory
STD Store (Long) 64 Transfer from floating-point register to
memory
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. (Table can be found on page 428 in textbook.)
+  Most machines provide the basic arithmetic
operations of add, subtract, multiply, and divide

 These are provided for signed integer (fixed-

point) numbers

 Often they are also provided for floating-point

and packed decimal numbers

 Other possible operations include a variety of

single-operand instructions:
 Absolute Arithmetic
 Take the absolute value of the operand
 Negate
 Negate the operand
 Increment
 Add 1 to the operand
Decrement
 Subtract 1 from the operand

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Table 12.6
Basic Logical Operations

P Q NOT P P AND Q P OR Q P XOR Q P=Q

0 0 1 0 0 0 1
0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 1 0 1 1 0 1

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0

(a) Logical right shift

(b) Logical left shift

(c) Arithmetic right shift

(d) Arithmetic left shift

(e) Right rotate

(f) Left rotate

Figure 12.6 Shift and Rotate Operations

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Table 12.7

Examples of Shift and Rotate Operations

Input Operation Result

10100110 Logical right shift (3 bits) 00010100
10100110 Logical left shift (3 bits) 00110000
10100110 Arithmetic right shift (3 bits) 11110100
10100110 Arithmetic left shift (3 bits) 10110000
10100110 Right rotate (3 bits) 11010100
10100110 Left rotate (3 bits) 00110101

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Instructions that
change the
format or Conversion
operate on the
format of data

An example of a
more complex
editing
instruction is the
An example EAS/390
is converting Translate (TR)
from instruction
decimal to
binary

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+
Input/Output

 Variety of approaches taken:

 Isolated programmed I/O
 Memory-mapped programmed I/O
 DMA
 Use of an I/O processor

 Many implementations provide only a few I/O instructions,

with the specific actions specified by parameters, codes, or
command words

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System Control

Instructions that can be executed only while the processor is in a

certain privileged state or is executing a program in a special
privileged area of memory

Typically these instructions are reserved for the use of the

operating system

Examples of system control operations:

A system control instruction An instruction to read or Access to process control

may read or alter a control modify a storage protection blocks in a
register key multiprogramming system

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+
Transfer of Control

 Reasons why transfer-of-control operations are required:

 It is essential to be able to execute each instruction more than
once
 Virtually all programs involve some decision making
 It helps if there are mechanisms for breaking the task up into
smaller pieces that can be worked on one at a time

 Most common transfer-of-control operations found in

instruction sets:
 Branch
 Skip
 Procedure call

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Memory
address Instruction

200
201
202 SUB X, Y
203 BRZ 211
Unconditional
branch Conditional
branch
210 BR 202
211

225 BRE R1, R2, 235

Conditional
branch
235

Figure 12.7 Branch Instructions

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Skip Instructions

Typically implies that one

instruction be skipped,
Includes an implied thus the implied address
address equals the address of the
next instruction plus one
instruction length

Because the skip

instruction does not Example is the
require a destination increment-and-skip-if-
address field it is free to zero (ISZ) instruction
do other things

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+
Procedure Call Instructions
 Self-contained computer program that is incorporated into a
larger program
 At any point in the program the procedure may be invoked, or called
 Processor is instructed to go and execute the entire procedure and
then return to the point from which the call took place

 Two principal reasons for use of procedures:

 Economy
 A procedure allows the same piece of code to be used many times
 Modularity

 Involves two basic instructions:

 A call instruction that branches from the present location to the
procedure
 Return instruction that returns from the procedure to the place from
which it was called

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Addresses Main Memory
4000

Main
4100 CALL Proc1
4101 Program

4500

4600 CALL Proc2

4601 Procedure
4650 CALL Proc2 Proc1
4651

RETURN

4800
Procedure
Proc2

RETURN

(a) Calls and returns (b) Execution sequence

Figure 12.8 Nested Procedures

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4601 4651
4101 4101 4101 4101 4101

(a) Initial stack (b) After (c) Initial (d) After (e) After (f) After (g) After
contents CALL Proc1 CALL Proc2 RETURN CALL Proc2 RETURN RETURN

Figure 12.9 Use of Stack to Implement Nested Procedures of Figure 12.8

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y2 Stack
Pointer
y1

Old Frame Pointer Frame

Pointer
Q: Return Point
Stack
x2 x2
Pointer

x1 x1

Old Frame Pointer Frame Old Frame Pointer

Pointer

P: Return Point P: Return Point

(a) P is active (b) P has called Q

Figure 12.10 Stack Frame Growth Using Sample Procedures P and Q

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+
x86 Operation Types
 The x86 provides a complex array of operation types including a
number of specialized instructions

 The intent was to provide tools for the compiler writer to produce
optimized machine language translation of high-level language
programs

 Provides four instructions to support procedure call/return:

 CALL
 ENTER
 LEAVE
 RETURN

 When a new procedure is called the following must be performed upon

entry to the new procedure:
 Push the return point on the stack
 Push the current frame pointer on the stack
 Copy the stack pointer as the new value of the frame pointer
 Adjust the stack pointer to allocate a frame

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Table 12.8
x86 Status Flags

Status Bit Name Description

CF Carry Indicates carrying or borrowing out of the left-most bit position
following an arithmetic operation. Also modified by some of
the shift and rotate operations.
PF Parity Parity of the least-significant byte of the result of an arithmetic
or logic operation. 1 indicates even parity; 0 indicates odd
parity.
AF Auxiliary Carry Represents carrying or borrowing between half-bytes of an 8-bit
arithmetic or logic operation. Used in binary-coded decimal
arithmetic.
ZF Zero Indicates that the result of an arithmetic or logic operation is 0.
SF Sign Indicates the sign of the result of an arithmetic or logic
operation.
OF Overflow Indicates an arithmetic overflow after an addition or subtraction
for twos complement arithmetic.
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Symbol Condition Tested Comment
A, NBE CF=0 AND ZF=0 Above; Not below or equal (greater than,
unsigned)
AE, NB, NC CF=0 Above or equal; Not below (greater than or

Table
equal, unsigned); Not carry
B, NAE, C CF=1 Below; Not above or equal (less than,

12.9
unsigned); Carry set
BE, NA CF=1 OR ZF=1 Below or equal; Not above (less than or
equal, unsigned)
E, Z ZF=1 Equal; Zero (signed or unsigned)
G, NLE [(SF=1 AND OF=1) OR (SF=0 Greater than; Not less than or equal (signed) x86
and OF=0)] AND [ZF=0]
Condition
GE, NL (SF=1 AND OF=1) OR (SF=0 Greater than or equal; Not less than (signed)
AND OF=0) Codes
L, NGE (SF=1 AND OF=0) OR (SF=0
AND OF=1)
Less than; Not greater than or equal (signed) for
LE, NG (SF=1 AND OF=0) OR (SF=0 Less than or equal; Not greater than (signed) Conditional
NE, NZ
AND OF=1) OR (ZF=1)
ZF=0 Not equal; Not zero (signed or unsigned)
Jump
NO OF=0 No overflow and
NS SF=0 Not sign (not negative) SETcc
NP, PO PF=0 Not parity; Parity odd Instructions
O OF=1 Overflow
P PF=1 Parity; Parity even
(Table can be found on page
S SF=1 Sign (negative) 440 in the textbook.)
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Category Instruction Description
PADD [B, W, D] Parallel add of packed eight bytes, four 16-bit words, or two 32-bit
doublewords, with wraparound.
PADDS [B, W] Add with saturation.
PADDUS [B, W] Add unsigned with saturation
PSUB [B, W, D] Subtract with wraparound.
PSUBS [B, W] Subtract with saturation.
Arithmetic PSUBUS [B, W] Subtract unsigned with saturation
PMULHW Parallel multiply of four signed 16-bit words, with high-order 16

PMULLW
bits of 32-bit result chosen.
Parallel multiply of four signed 16-bit words, with low-order 16 bits
of 32-bit result chosen.
Table 12.10
PMADDWD Parallel multiply of four signed 16-bit words; add together adjacent
pairs of 32-bit results.
PCMPEQ [B, W, D] Parallel compare for equality; result is mask of 1s if true or 0s if
Comparison
PCMPGT [B, W, D]
false.
Parallel compare for greater than; result is mask of 1s if true or 0s if
false.
MMX
PACKUSWB
PACKSS [WB, DW]
Pack words into bytes with unsigned saturation.
Pack words into bytes, or doublewords into words, with signed Instruction Set
saturation.
Conversion PUNPCKH [BW, WD, Parallel unpack (interleaved merge) high-order bytes, words, or
DQ] doublewords from MMX register.
PUNPCKL [BW, WD, Parallel unpack (interleaved merge) low-order bytes, words, or
DQ] doublewords from MMX register.
PAND 64-bit bitwise logical AND
Logical PNDN 64-bit bitwise logical AND NOT
POR 64-bit bitwise logical OR
PXOR 64-bit bitwise logical XOR
PSLL [W, D, Q] Parallel logical left shift of packed words, doublewords, or
quadword by amount specified in MMX register or immediate
value.
Shift PSRL [W, D, Q] Parallel logical right shift of packed words, doublewords, or
quadword.
PSRA [W, D] Parallel arithmetic right shift of packed words, doublewords, or
quadword. (Table can be found on page
Data Transfer MOV [D, Q] Move doubleword or quadword to/from MMX register.
442 in the textbook.)
State Mgt EMMS Empty MMX state (empty FP registers tag bits).
Note: If an instruction supports multiple data types [byte (B), word (W), doubleword (D), quadword
(Q)], the data types are indicated in brackets.
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+
x86 Single-Instruction, Multiple-
Data (SIMD) Instructions
 1996 Intel introduced MMX technology into its Pentium
product line
 MMX is a set of highly optimized instructions for multimedia tasks

 Video and audio data are typically composed of large arrays

of small data types

 Three new data types are defined in MMX

 Packed byte
 Packed word
 Packed doubleword

 Each data type is 64 bits in length and consists of multiple

smaller data fields, each of which holds a fixed-point integer

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ARM Operation Types

Load and store Branch Data-processing

instructions instructions instructions

Parallel addition
Multiply Extend
and subtraction
instructions instructions
instructions

Status register
access
instructions
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Code Symbol Condition Tested Comment
0000 EQ Z=1 Equal
0001 NE Z=0 Not equal
0010 CS/HS C=1 Carry set/unsigned higher or same
0011 CC/LO C=0 Carry clear/unsigned lower
0100 MI N=1 Minus/negative Table 12.11
0101 PL N=0 Plus/positive or zero
0110
0111
VS
VC
V=1
V=0
Overflow
No overflow
ARM
1000 HI C = 1 AND Z = 0 Unsigned higher Conditions
1001 LS C = 0 OR Z = 1 Unsigned lower or same for
1010 GE N=V Signed greater than or equal Conditional
[(N = 1 AND V = 1)
OR (N = 0 AND V = 0) Instruction
1011 LT N≠V Signed less than Execution
[(N = 1 AND V = 0)
OR (N = 0 AND V = 1)]
1100 GT (Z = 0) AND (N = V) Signed greater than
1101 LE (Z = 1) OR (N ≠ V) Signed less than or equal
1110 AL — Always (unconditional)
(Table can be found on
1111 — — This instruction can only be executed
Page 445 in the textbook.)
unconditionally

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+ Summary Instruction Sets:
Characteristics and
Chapter 12 Functions

 Machine instruction  Intel x86 and ARM data types

characteristics
 Types of operations
 Elements of a machine
instruction  Data transfer
 Instruction representation  Arithmetic
 Instruction types  Logical
 Number of addresses  Conversion
 Instruction set design  Input/output
 Types of operands  System control
 Numbers  Transfer of control
 Characters
 Logical data  Intel x86 and ARM operation
types
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+

William Stallings
Computer Organization
and Architecture
10th Edition
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NJ. All rights reserved.
+ Chapter 13
Instruction Sets: Addressing
Modes and Formats

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Addressing Modes
Immediate

Direct

Indirect

Register

Register indirect

Displacement

Stack

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Instruction Instruction Instruction
Operand A A
Memory Memory

Operand

Operand

(a) Immediate (b) Direct (c) Indirect

Instruction Instruction Instruction

R R R A
Memory Memory

Operand

Operand Operand
Registers Registers Registers
(d) Register (e) Register Indirect (f) Displacement

Instruction

Implicit

Top of Stack
Register

(g) Stack

Figure 13.1 Addressing Modes

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Table 13.1
Basic Addressing Modes
Mode Algorithm Principal Advantage Principal Disadvantage
Immediate Operand = A No memory reference Limited operand magnitude
Direct EA = A Simple Limited address space
Indirect EA = (A) Large address space Multiple memory references
Register EA = R No memory reference Limited address space
Register indirect EA = (R) Large address space Extra memory reference
Displacement EA = A + (R) Flexibility Complexity
Stack EA = top of stack No memory reference Limited applicability

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+ Immediate Addressing

 Simplest form of addressing

 Operand = A

 This mode can be used to define and use constants or set initial
values of variables
 Typically the number will be stored in twos complement form
 The leftmost bit of the operand field is used as a sign bit

 Advantage:
 No memory reference other than the instruction fetch is required to
obtain the operand, thus saving one memory or cache cycle in the
instruction cycle

 Disadvantage:
 The size of the number is restricted to the size of the address field, which,
in most instruction sets, is small compared with the word length

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Direct Addressing

Address field
contains the
effective address of
the operand

Effective address
(EA) = address field
(A)

Was common in
earlier generations
of computers

Requires only one

memory reference
and no special
calculation

Limitation is that it
provides only a
limited address
space

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+
Indirect Addressing

 Reference to the address of a word in memory which contains a

full-length address of the operand

 EA = (A)
 Parentheses are to be interpreted as meaning contents of

 Advantage:
 For a word length of N an address space of 2N is now available

 Disadvantage:
 Instruction execution requires two memory references to fetch the operand
 One to get its address and a second to get its value

 A rarely used variant of indirect addressing is multilevel or cascaded

indirect addressing
 EA = ( . . . (A) . . . )
 Disadvantage is that three or more memory references could be required
to fetch an operand

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Register Addressing

Address field
refers to a
register rather EA = R
than a main
memory address

Advantages: Disadvantage:
• Only a small • The address space
address field is is very limited
needed in the
instruction
• No time-consuming
memory references
are required

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+
Register Indirect Addressing

 Analogous to indirect addressing

 The only difference is whether the address field refers to a
memory location or a register

 EA = (R)

 Address space limitation of the address field is overcome by

having that field refer to a word-length location containing an
address

 Uses one less memory reference than indirect addressing

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+
Displacement Addressing

 Combines the capabilities of direct addressing and register

indirect addressing

 EA = A + (R)

 Requires that the instruction have two address fields, at least one
of which is explicit
 The value contained in one address field (value = A) is used directly
 The other address field refers to a register whose contents are added
to A to produce the effective address

 Most common uses:

 Relative addressing
 Base-register addressing
 Indexing

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Relative Addressing

The implicitly referenced register is the program counter (PC)

• The next instruction address is added to the address field to produce the EA
• Typically the address field is treated as a twos complement number for this
operation
• Thus the effective address is a displacement relative to the address of the
instruction

Exploits the concept of locality

Saves address bits in the instruction if most memory references

are relatively near to the instruction being executed

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+
Base-Register Addressing

 The referenced register contains a main memory address and

the address field contains a displacement from that address

 The register reference may be explicit or implicit

 Exploits the locality of memory references

 Convenient means of implementing segmentation

 In some implementations a single segment base register is

employed and is used implicitly

 In others the programmer may choose a register to hold the

base address of a segment and the instruction must reference it
explicitly

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Indexing
 The address field references a main memory address and the referenced
register contains a positive displacement from that address

 The method of calculating the EA is the same as for base-register addressing

 An important use is to provide an efficient mechanism for performing

iterative operations

 Autoindexing
 Automatically increment or decrement the index register after each reference to it
 EA = A + (R)
 (R)  (R) + 1

 Postindexing
 Indexing is performed after the indirection
 EA = (A) + (R)

 Preindexing
 Indexing is performed before the indirection
 EA = (A + (R))

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+
Stack Addressing

 A stack is a linear array of locations

 Sometimes referred to as a pushdown list or last-in-first-out queue

 A stack is a reserved block of locations

 Items are appended to the top of the stack so that the block is partially filled

 Associated with the stack is a pointer whose value is the address of the top of
the stack
 The stack pointer is maintained in a register
 Thus references to stack locations in memory are in fact register indirect addresses

 Is a form of implied addressing

 The machine instructions need not include a memory

reference but implicitly operate on the top of the stack

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Table 13.2
x86 Addressing Modes
Mode Algorithm
Immediate Operand = A
Register Operand LA = R
Displacement LA = (SR) + A
Base LA = (SR) + (B)
Base with Displacement LA = (SR) + (B) + A
Scaled Index with Displacement LA = (SR) + (I) ´ S + A
Base with Index and Displacement LA = (SR) + (B) + (I) + A
Base with Scaled Index and Displacement LA = (SR) + (I) ´ S + (B) + A
Relative LA = (PC) + A
LA = linear address
(X) = contents of X
SR = segment register
PC = program counter
A = contents of an address field in the instruction
R = register
B = base register
I = index register
S = scaling factor
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STRB r0, [r1, #12]

Offset
0xC 0x20C 0x5
r0 Destination
0x5 register
r1 for STR
Original
base register
0x200 0x200

(a) Offset

STRB r0, [r1, #12]!

r1 Offset
Updated
base register 0x20C 0xC 0x20C 0x5
r0 Destination
0x5 register
r1 for STR
Original
base register
0x200 0x200

(b) Preindex

STRB r0, [r1], #12

r1 Offset
Updated
base register 0x20C 0xC 0x20C
r0 Destination
0x5 register
r1 for STR
Original
base register
0x200 0x200 0x5

(c) Postindex

Figure 13.3 ARM Indexing Methods

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+ ARM Data Processing Instruction Addressing
and Branch Instructions

 Data processing instructions

 Use either register addressing or a mixture of register and
immediate addressing
 For register addressing the value in one of the register operands
may be scaled using one of the five shift operators

 Branch instructions
 The only form of addressing for branch instructions is immediate
 Instruction contains 24 bit value
 Shifted 2 bits left so that the address is on a word boundary
 Effective range ± 32MB from from the program counter

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LDMxx r10, {r0, r1, r4}
STMxx r10, {r0, r1, r4}
Increment Increment Decrement Decrement
after (IA) before (IB) after (DA) before (DB)
r10
Base register 0x20C (r4) 0x218
(r4) (r1) 0x214
(r1) (r0) 0x210
(r0) (r4) 0x20C
(r1) (r4) 0x208
(r0) (r1) 0x204
(r0) 0x200

Figure 13.4 ARM Load/Store Multiple Addressing

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Instruction Formats

Must include
Define the
an opcode For most
layout of the
and, implicitly instruction
bits of an
or explicitly, sets more than
instruction, in
indicate the one
terms of its
addressing instruction
constituent
mode for each format is used
fields
operand

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+
Instruction Length
 Most basic design issue

 Affects, and is affected by:

 Memory size
 Memory organization
 Bus structure
 Processor complexity
 Processor speed

 Should be equal to the memory-transfer length or one should

be a multiple of the other

 Should be a multiple of the character length, which is usually

8 bits, and of the length of fixed-point numbers

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Allocation of Bits

Number of Register
Number of
addressing versus
operands
modes memory

Number of Address Address

register sets range granularity

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Memory Reference Instructions
Opcode D/I Z/C Displacement
0 2 3 4 5 11

Input/Output Instructions
1 1 0 Device Opcode
0 2 3 8 9 11

Register Reference Instructions

Group 1 Microinstructions
1 1 1 0 CLA CLL CMA CML RAR RAL BSW IAC
0 1 2 3 4 5 6 7 8 9 10 11

Group 2 Microinstructions
1 1 1 1 CLA SMA SZA SNL RSS OSR HLT 0
0 1 2 3 4 5 6 7 8 9 10 11

Group 3 Microinstructions
1 1 1 1 CLA MQA 0 MQL 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11

D/I = Direct/Indirect address IAC = Increment ACcumulator

Z/C = Page 0 or Current page SMA = Skip on Minus Accumulator
CLA = Clear Accumulator SZA = Skip on Zero Accumulator
CLL = Clear Link SNL = Skip on Nonzero Link
CMA = CoMplement Accumulator RSS = Reverse Skip Sense
CML = CoMplement Link OSR = Or with Switch Register
RAR = Rotate Accumultator Right HLT = HaLT
RAL = Rotate Accumulator Left MQA = Multiplier Quotient into Accumulator
BSW = Byte SWap MQL = Multiplier Quotient Load

Figure 13.5 PDP-8 Instruction Formats

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Index
Opcode Register I Memory Address
Register
0 8 9 12 14 17 18 35

I = indirect bit

Figure 13.6 PDP-10 Instruction Format

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+
Variable-Length Instructions

 Variations can be provided efficiently and compactly

 Increases the complexity of the processor

 Does not remove the desirability of making all of the

instruction lengths integrally related to word length
 Because the processor does not know the length of the next
instruction to be fetched a typical strategy is to fetch a number of
bytes or words equal to at least the longest possible instruction
 Sometimes multiple instructions are fetched

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1 Opcode Source Destination 2 Opcode R Source 3 Opcode Offet
4 6 6 7 3 6 8 8

4 Opcode FP Destination 5 Opcode Destination 6 Opcode CC

8 2 6 10 6 12 4

7 Opcode R 8 Opcode
13 3 16

9 Opcode Source Destination Memory Address

4 6 6 16

10 Opcode R Source Memory Address

7 3 6 16

11 Opcode FP Source Memory Address

8 2 6 16

12 Opcode Destination Memory Address

10 6 16

13 Opcode Source Destination Memory Address 1 Memory Address 2

4 6 6 16 16

Numbers below fields indicate bit length

Source and Destination each contain a 3-bit addr essing mode field and a 3-bit register number
FP indicates one of four floating-point registers
R indicates one of the general-purpose r egisters
CC is the condition code field

Figure 13.7 Instruction Formats for the PDP-11

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Hexadecimal Explanation Assembler Notation
Format and Description

8 bits
0 5 Opcode for RSB RSB
Return from subroutine

D 4 Opcode for CLRL CLRL R9

5 9 Register R9 Clear register R9

B 0 Opcode for MOVW MOVW 356(R4), 25(R11)

Word displacement mode,
C 4 Register R4
Move a word from address
that is 356 plus contents
6 4 356 in hexadecimal of R4 to address that is
0 1 25 plus contents of R11
Byte displacement mode,
A B Register R11
1 9 25 in hexadecimal

C 1 Opcode for ADDL3 ADDL3 #5, R0, @A[R2]

0 5 Short literal 5 Add 5 to a 32-bit integer in

R0 and store the result in
5 0 Register mode R0
location whose address is
4 2 Index prefix R2 sum of A and 4 times the
Indirect word relative contents of R2
D F (displacement from PC)

Amount of displacement from

PC relative to location A

Figure 13.8 Examples of VAX Instructions

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0 or 1 0 or 1 0 or 1 0 or 1
bytes bytes bytes bytes
Operand Address
Instruction Segment
size size
prefix override
override override

0 or 1 0 or 1
0, 1, 2, 3, or 4 bytes 1, 2, or 3 bytes bytes bytes 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes

Instruction prefixes Opcode ModR/m SIB Displacement Immediate

Mod Reg/Opcode R/M Scale Index Base

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Figure 13.9 x86 Instruction Format

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+
Thumb-2 Instruction Set

 The only instruction set available on the Cortex-M microcontroller

products

 Is a major enhancement to the Thumb instruction set architecture (ISA)

 Introduces 32-bit instructions that can be intermixed freely with the older 16-
bit Thumb instructions
 Most 32-bit Thumb instructions are unconditional, whereas almost all ARM
instructions can be conditional
 Introduces a new If-Then (IT) instruction that delivers much of the functionality
of the condition field in ARM instructions

 Delivers overall code density comparable with Thumb, together with the
performance levels associated with the ARM ISA

 Before Thumb-2 developers had to choose between Thumb for size and
ARM for performance

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Address Contents Address Contents
101 0010 0010 101 2201 101 2201
102 0001 0010 102 1202 102 1202
103 0001 0010 103 1203 103 1203
104 0011 0010 104 3204 104 3204

201 0000 0000 201 0002 201 0002

202 0000 0000 202 0003 202 0003
203 0000 0000 203 0004 203 0004
204 0000 0000 204 0000 204 0000

(a) Binary program (b) Hexadecimal program

Address Instruction Label Operation Operand

101 LDA 201 FORMUL LDA I
102 ADD 202 ADD J
103 ADD 203 ADD K
104 STA 204 STA N

201 DAT 2 I DATA 2

202 DAT 3 J DATA 3
203 DAT 4 K DATA 4
204 DAT 0 N DATA 0

(c) Symbolic program (d) Assembly program

Figure 13.14 Computation of the Formula N = I + J+ K

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+ Summary Instruction Sets:
Addressing Modes
and Formats
Chapter 13
 x86 addressing modes
 Addressing modes
 ARM addressing modes
 Immediate addressing
 Direct addressing  Instruction formats
 Indirect addressing  Instruction length
 Register addressing  Allocation of bits
 Register indirect addressing  Variable-length instructions
 Displacement addressing
 X86 instruction formats
 Stack addressing
 ARM instruction formats
 Assembly language

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