CHAPTER 4

THE CENTRAL PROCESSING

UNIT (CPU)

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Outline
3.1 Introduction
 What is an Instruction Set ?
 3.2 Machine Instruction Characteristics
 Elements of Machine Instruction
 Operand Locations
 Instruction Representation
 Instruction Types
 3.3 Instruction Set Design
 Types of Operands
 Types of Operations
 Addressing Mode
 Instruction Format
 3.4 Instruction Cycle Revisited
 3.5 Instruction Cycle Data Flow
 3.6 Processor Structure and Function
 Processor Organization
 Register Organization
 3.7 Reading Assignment
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1. INTRODUCTION
Much of the computer architecture/organization is hidden
from a high level language programmer
Shouldn’t care what the underlying architecture really is

What is an instruction set?

the collection of different instructions that are understood
by a CPU or that the CPU can execute
Machine Code
encoded in binary – for machines to work with

For people: represent by assembly codes3

text – for people to work with
Cont.….
Instruction set is a boundary where
Computer designer and computer programmer can view the same machine
From Designer’s Point of view
It provides the functional requirements for the CPU.
Implementing the CPU is a task that in large part involves implementing the machine
instruction set.
From Assembly Language Programmer’s Point of view
It enables to be aware of the register and memory structure,
the types of data directly supported by the machine and
the functioning of the ALU
3.2 MACHINE INSTRUCTION CHARACTERISTICS
The operation of the CPU is determined by the instructions it executes

We will investigate

the design of the instruction set
The impact of the set on the design of the overall computer system
ELEMENTS OF A MACHINE INSTRUCTION

Each instruction must contain all the information required by the CPU for execution
These elements are :
Operation code (Op code)
 Specifies the operation to be performed
 Do this operation
Source Operand(s) reference(s)
 Specifies a register or memory location of operand data
 With this/these operands
 An operation may involve one or more source operands
 Inputs for the operation specified
ELEMENTS OF A MACHINE INSTRUCTION…

Result Operand reference

Where the result of the operation should be placed ?
Put the answer here
Next Instruction reference
From where to fetch the next instruction
When you have done that, do this...
In most cases not explicitly stated in the instruction
 Implicitly the next instruction, the one that logically follows the current one in
the program
OPERAND LOCATIONS

Where Can Operands Be?

Source and result operands can be in one of the four areas:
Main memory
 Memory address must be supplied
CPU register
 Implicitly referenced, if only one register exist
 Explicitly using its unique number, if more than one register exists
Immediate
 Operand contained in the instruction being executed
I/O device
 Specify the I/O device for the operation
INSTRUCTION REPRESENTATION

Within a computer, each instruction is represented by sequence of

bits
Each instruction has a unique bit pattern
Instruction divided into fields
Corresponding to the constituent elements of the instruction
E.g. A simple instruction format

With most instruction set, more than one format is used

SIMPLE INSTRUCTION FORMAT
INSTRUCTION REPRESENTATION…

Difficult for the programmers to deal with binary representation of

machine instruction
Hence, it is common to use a symbolic representation of machine instruction
Opcodes

 Represented by abbreviations called mnemonics --- that indicate the

operation
Operands

 Also represented symbolically

Example

ADD R, Y
It is possible to write a machine language program in symbolic form
A simple program accepts this symbolic input ,convert opcode and operand
references to binary form and construct binary machine instruction
INSTRUCTION TYPES
An instruction set must be functionally complete
Sufficient enough to express any of the instructions from a high
level language
Categories of instruction types
Data processing
 Arithmetic and logic instructions
Data storage
 Memory instructions
Data movement
I/O instructions
Control

 Test and branch instructions12

 Program flow and control
3.3 INSTRUCTION SET DESIGN
One of the most interesting and analysed aspects of computer design
A very complex task
Because it affects so many aspects of the computer system
Instruction set
Boundary where computer designer and Computer programmer
can view the same machine
Programmer’s means of controlling the CPU
Programmers requirement must be considered in designing the
instruction set
INSTRUCTION SET DESIGN …
Most important issues related to the design of instruction set includes:
Operation repertoire
 How many ops?
 What can they do?
 How complex are they?
Data Types
 Built-In Data types supported
Instruction formats
 How to encode as binary values
 Length of op code field
 Number of addresses
Registers

 Number of CPU registers available

Which operations can be performed on which registers? 14
Addressing modes
TYPES OF OPERAND
Machine instructions operate on data
Categories of data
 Numbers
 Signed Integer / Unsigned Integer / Floating Point
 Characters
 ASCII, Unicode etc.
 Logical Data
 Bits or flags
 A group of bit where each bit has information
 Addresses
 Addresses are, in fact, a form of data
 In many cases, some calculation must be performed on the operand reference in an
instruction to determine the memory address
In this context, addresses can be considered to be unsigned integers
Note: The “type” of a unit of data is determined by the operation being performed on it
TYPES OF OPERATIONS
Different machines support different opcodes:
Data Transfer
Arithmetic

Logical

Conversion

I/O

System Control
Transfer of Control
DATA TRANSFER

Most fundamental type of instructions

Must specify the following things
Location of source and destination operands
 memory, register …
Length of data to be transferred
 Full word, half word …
Addressing mode of each operand
E.g.

 Move, Store, Load, Push, Pop

In terms of CPU action
data transfer operations are the simplest type
ARITHMETIC
o Performed by ALU
o Basic arithmetic operations provided by most machines are:
Add, Subtract, Multiply, Divide
 Signed Integer
 Floating point

o May include
o Increment
o Decrement
o Negate
o Absolute
LOGICAL
Operations that manipulate individual bits of a word
Bitwise operations
 AND, OR, exclusive-OR (XOR)
 NOT (one’s complement)
In addition a variety of shifting and rotating functions
Logical shift
 Shifts bits of word either to the left or right
 On one end the bit shifted out is lost
Arithmetic shift
 Treats the data as a signed integer and does not shift the sign bit
Rotate/Cyclic shift
 Preserves all of the bits being operated on
SHIFT AND ROTATE OPERATIONS
.
logical shift shift in 0

Arithmetic shift keep sign !

Rotate
CONVERSION

Change the format of data or operate on the format of

data
Binary to Decimal
ASCII to EBCDIC

E.g. Binary to BCD

binary 00001111 (1510)
packed BCD 0001 0101
1 5
INPUT/OUTPUT
Transfer data
from the computer to peripheral devices
From peripheral devices to the computer system

To be seen in detail in another chapter

SYSTEM CONTROL
Reserved for use by the operating system
Instructions executed while the processor is in certain privileged mode
Privileged instructions
CPU needs to be in specific state

TRANSFER OF CONTROL
Alter the flow of program
i.e. change the sequence of instruction execution
Update the PC to a specific address
Most common such type of operations are:
Branch, Skip, Procedure call
TRANSFER OF CONTROL…
Branch
• Also called jump instruction
• Its operand is the address of the next instruction to be fetched
and executed
Two types of branches
Conditional and Unconditional

Conditional Branch
A branch is made if certain condition is met
E.g.
BRP X
Branch to instruction at location X if result is positive
BRZ X
Branch to instruction at location X if result is zero
BRE R1,R2,X
Branch to X if contents of R1 is equal to contents of R2

Unconditional branch
E.g.
BR X
Branch to instruction at location X
TRANSFER OF CONTROL…
Branch Instructions
TRANSFER OF CONTROL …
Skip

Implies that the next instruction be skipped

Contains an implied address
Can be of two types:
 Unconditional
 Skip (i.e. unconditionally increment PC to skip the next instruction)
 Conditional
 Test some condition and skip if met/satisfied
 E.g. Increment and skip next instruction if result is zero
ISZ R1  increment & skip if zero
Branch X  skip this if result was zero ADD A
Procedure call
[Reading Assignment]
TRANSFER OF CONTROL …
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TRANSFER OF CONTROL …

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TRANSFER OF CONTROL …
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TRANSFER OF CONTROL …

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ADDRESSING MODES
The manner in which each address field specify operand location
Notations:

A = Contents of an address field in the instruction

R = Contents of an address field in the instruction that refers to a register
(X) = Contents of memory location X or register X
EA =Effective address of the location containing the referenced operand
Note:

Virtually all computer architectures provide more than one type addressing
modes
The processor can used different approaches to determine which addressing mode
is being used in a particular instruction
Different opcodes will use different addressing modes
One or more bits in the instruction format can be used as a mode field
Determines which addressing mode is to be used
ADDRESSING MODES…

Types of addressing modes

Immediate e.g.?

Direct e.g.?

Indirect e.g.?

Register e.g.?

Register Indirect e.g.?

Displacement e.g.?

Stack e.g.?
IMMEDIATE ADDRESSING
The instruction itself contains the operands value
Operand is part of instruction
Operand =A
E.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No additional memory reference required after the fetch of the
instruction itself
The value that can be specified is limited
Size/value of the operand is limited/limited range
Fast
IMMEDIATE ADDRESSING DIAGRAM
. Opcode Operand

DIRECT ADDRESSING
Address field contains address of operand
Effective address EA = A
Operand = (A)
E.g. ADD A
 Add contents of memory location A to accumulator
One more memory access needed to fetch the operand
No additional calculations required to work out effective address
Number of memory locations that can be referenced, limited, due to
limited width of the field
Limited address space
Common on earlier generation of computers
DIRECT ADDRESSING DIAGRAM
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INDIRECT ADDRESSING
A (the address field) refers to a memory location which contains the
address of operand
Multiple (two) memory accesses to find operand
Fetch EA
Fetch operand
 Access the memory twice, hence slower
EA = (A)
Operand = ((A))
E.g. ADD (A)
 Look in A, find address (A) and look there for operand
Range of EA increased
Large address space
2n ,where n = word length
INDIRECT ADDRESSING DIAGRAM
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REGISTER ADDRESSING
Similar to direct addressing
The address field refers to a register than a main memory address
EA = R
Operand = (R )
Very small address field needed
Shorter instructions
Faster instruction fetch
No memory access required
Very fast execution
Very limited address space
Small number of registers can be referenced
REGISTER ADDRESSING DIAGRAM
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REGISTER INDIRECT ADDRESSING
Similar to indirect addressing mode
Operand is in memory pointed to by contents of register R
EA = (R)
Operand =((R ))
Large address space (2n)
Where n is the width of the register
Address space limitation overcome
Uses one less memory access than indirect addressing
REGISTER INDIRECT ADDRESSING
DIAGRAM
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DISPLACEMENT ADDRESSING
Very powerful addressing mode
Combines

direct addressing and

Register indirect addressing
Instruction needs to have two address fields
At least one of which is explicit
EA = A + (R)
Address field hold two values
A = base value
R = register that holds displacement
or vice versa
DISPLACEMENT ADDRESSING DIAGRAM
.
RELATIVE ADDRESSING MODE
A version of displacement addressing mode
Implicitly references the PC register
R = Program counter, PC
EA = A + (PC)
Saves bits
BASE-REGISTER ADDRESSING

Referenced register contains memory address

R holds pointer to base address
Address field contains the displacement from that address
A holds displacement
Exploits locality of memory references
INDEXED ADDRESSING MODE
Address field contains memory address
A = base
The referenced register contains a displacement from that address
R = displacement
EA =A+(R)
Good for accessing arrays and performing iterative
operations
Auto indexing
 increment and decrement
INDEXED ADDRESSING…
Combinations

Indirect addressing with indexing

Post indexing
The indexing performed after the indirection
EA = (A) + (R)
Good to access a block of data of a fixed format
Pre indexing
The indexing performed before the indirection
EA = (A+(R))
Used to construct a multiway branch table
STACK ADDRESSING MODE
A stack
The stack mode of addressing is a form of implied addressing
The machine instructions need not include a memory reference but
implicitly operate on the top of the stack
ADDRESSING MODES SUMMARY
INSTRUCTION FORMAT

It defines the layout of the bits of an instruction, in terms of its constituent parts
More that one format used in a given instruction set
What are the factors affecting the instruction format ?
READING ASSIGNMENT!!!
3.4 INSTRUCTION CYCLE REVISITED
Instruction cycle so far consists of the following sub cycles:
Fetch

Execute

Interrupt

Additional sub cycle to be added:

Indirect cycle
INSTRUCTION CYCLE ,REVISED …
Indirect addressing
May require memory access to fetch operands
Indirect addressing requires more memory accesses
Can be thought of as additional instruction sub cycle
3.5 INSTRUCTION CYCLE DATA FLOW
The exact sequence of events during an instruction cycle
depends on the design of the CPU

In general terms, assuming a CPU that employs the following

registers
MAR

MBR

PC

IR

The possible Data Flow is indicated next

DATA FLOW (INSTRUCTION FETCH)
Fetch

PC contains address of next instruction

Address moved to MAR
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to MBR, then to IR
Meanwhile PC incremented by 1
DATA FLOW (FETCH DIAGRAM)
.
DATA FLOW (DATA FETCH)
IR is examined
If indirect addressing, indirect cycle is performed
Right most N bits of MBR transferred to MAR
Control unit requests memory read
Result (address of operand) moved to MBR
DATA FLOW (INDIRECT DIAGRAM)
DATA FLOW (EXECUTE)
May take many forms
Depends on instruction being executed
May include
Memory read/write
Input/Output

Register transfers
ALU operations
DATA FLOW (INTERRUPT)
Simple and Predictable
Current PC saved to allow resumption after interrupt
Contents of PC copied to MBR
Special memory location (e.g. stack pointer) loaded to MAR
MBR written to memory
PC loaded with address of interrupt handling routine
Next instruction (first of interrupt handler) can be fetched
DATA FLOW (INTERRUPT DIAGRAM)
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3.6 Processor Structure and Function
Processor Organization
To understand the organization of the CPU, recall the
requirements placed on the CPU:
Fetch instruction
Interpret instruction
Fetch data
Process data
Write data
To do all these things
Processor needs to store data temporarily
 Temporary data storage locations --- Registers --- are needed
PROCESSOR ORGANIZATION…
Simplified view of a CPU
Indicates its connection to the system via the system bus
PROCESSOR ORGANIZATION…
Detailed view of a CPU
Indicates

Data transfer and logic control paths

Internal processor bus
 Used to transfer data b/n the ALU and various registers
REGISTER ORGANIZATION
Registers

CPU must have some working space

 Temporary storage
Top level of memory hierarchy
Number and function vary between processor designs
One of the major design decisions
REGISTER ORGANIZATION…
Registers classified into two groups:
User visible registers:
 Can be referenced by assembly language instructions
Control and status registers:
 Used by control unit to control the operation of the CPU
USER VISIBLE REGISTERS
Can be categorized as follows:
General purpose registers
Data registers
Address registers
Condition codes

USER VISIBLE REGISTERS…

General Purpose Registers
Can be assigned variety of function by the programmer
May be true general purpose
May be restricted
May be used for data or addressing
Data Registers
Used only to hold data
Accumulator
USER VISIBLE REGISTERS…
Address registers
Hold addresses
Can be
 General purpose or
 Devoted to particular addressing mode
 Index registers, stack pointer, segment register

CONDITION CODES
Sets of individual bits , also called flags
Each bit set by CPU hardware as the result of operations:
E.g. Arithmetic operation results could be
 Positive, negative, zero, overflow
Can be read (implicitly) by programs
e.g. Jump if zero
Can not (usually) be set by programs
CONTROL & STATUS REGISTERS

Refers to different registers employed to control the operation of the CPU

Most not visible to the user
Register essential during instruction cycle are
Program Counter (PC)
Instruction Register (IR)
Memory Address Register (MAR)
Memory Buffer Register (MBR)
CONTROL & STATUS REGISTERS…
Program Status Word (PSW)
A register that contain status information
Usually contains
Condition codes
Status information
Common fields or flags include
Sign, zero, carry, equal, overflow, supervisor, interrupt enable/disable
Note that CPU design and Operating system design are closely linked
End of Chapter
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