Introduction to Microprocessors, Module 1,Dept of CSE

Module I the Processor 8086

Register organization of 8086, architecture, signal description of 8086,

physical memory organization, I/O addressing capability, minimum mode
8086 system and timings, maximum mode 8086system and timings.

Microprocessor: It is an IC with all the functions of a CPU however, it

cannot be used stand alone since unlike a microcontroller it has no memory
or peripherals. It is a multipurpose, programmable, clock-driven, register-
based electronic device that reads binary instructions from a storage device
called memory, accepts binary data as input and processes data according
to those instructions and provide results as output.

Microprocessors can be classified based on the data bus width

❖ 4-Bit Microprocessors
❖ 8-Bit Microprocessors
❖ 16-Bit Microprocessors
❖ 32-Bit Microprocessors
❖ 64-Bit Microprocessors

History:

Microproce Bata Bus Pins No.Of

ssor transi
Intel
4004 4-bit 640 bytes 16 2300 1971
8008 8-bit 16KB 18 3500
8080 8-bit 64KB 40 6000
8085 8-bit 64KB 40 1976
8086 16-bit 1MB 40 29000 1978
8088 8/16 bit 1MB 40 1979
80186 16-bit 1MB 68 1982
80286 16-bit 16MB real, 4 68 134000 1982
GB Virtual
80386 32-bit 4GB real, 132 PGA 275000 1986
64TB virtual
80486 32-bit 4GB real, 168 PGA 1200000 1989
64TB virtual
Pentium 64-bit 4GB real l 273 PGA 3.1 1993
Million
Pentium 64-bit 64 GB real 5.5 1995
pro Million
Pentium II 64-bit 64 GB real 7.5 1997

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 1

Introduction to Microprocessors, Module 1,Dept of CSE

Million
Pentium II 64-bit 1998
XEON
Pentium III 64-bit 1999
Pentium 64-bit 2000
IV
Dual Core 64-bit 2006
Core 2 2006
Core i7 2008
Core i5 2009
Core i3 2010
Motorola
6800 8-bit 64KB 40 1974
6809 8-bit 64KB 40 1978
68000 16-bit 16MB 64 1979
68020 32-bit 4GB 169 PGA 200000 1984
68030 32-bit 4GB 169 PGA
68040 32-bit 4GB
Zilog
z-80 8-bit 64KB 40
z-800 8-bit 500K
z-8000 16-bit 64KB

8086 features:

8086 is a 16-bit Integer processor packed in DIP (Dual Inline Packaged) IC

in a 40 pin.

8086 has 14 internal registers, each of 16 bits or 2 Bytes wide. The size of
the internal registers indicate how much information the processor can
operate on at a time and how it moves data around internally within the
chip, sometimes also referred to as the internal data bus.

8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store
intermediate values during execution. Each of these has two 8 bit parts
(higher and lower).

Architecture: The internal architecture of Intel 8086 is divided into 2 units:

❖ Bus Interface Unit (BIU)

❖ Execution Unit (EU)

These are explained as following below.

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Introduction to Microprocessors, Module 1,Dept of CSE

Fig: Architecture of 8086

1. Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the
System Bus. It performs memory read, I/O read etc. to transfer the data
between memory and I/O devices.

BIU performs the following functions-

• It generates the 20 bit physical address for memory access.

• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6 byte pre-fetch instruction queue (supports
pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a

pre-fetch queue and an Address Generation Circuit.

Instruction Pointer (IP):

• It is a 16 bit register. It holds offset of the next instructions in the

Code Segment.
• IP is incremented after every instruction byte is fetched.

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Introduction to Microprocessors, Module 1,Dept of CSE

• IP gets a new value whenever a branch instruction occurs.

• CS is multiplied by 10H to give the 20 bit physical address of the Code
Segment.
• Address of the next instruction is calculated as CS x 10H + IP.

Example:

CS = 4321H IP = 1000H
Then CS x 10H = 43210H + offset = 53210H

This is the address of the instruction.

Segment Registers: To complete 1Mbyte memory is divided into 16 logical

segments. With Each segment contains 64Kbyte of memory. There are four
segment registers.

Code Segment register: CS register is a 16-bit register containing address

of 64 KB segment with processor instructions. CS holds the base address for
the Code Segment. All programs are stored in the Code Segment and
accessed via the IP register. CS register cannot be changed directly. The CS
register is automatically updated during far jump, far call and far return
instructions. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.

Data Segment registers: Data segment (DS) register is a 16-bit register

containing address of 64KB segment with program data. DS holds the base
address for the Data Segment. By default, the processor assumes that all
data referenced by general registers (AX, BX, CX, DX) and index register (SI,
DI) is located in the data segment. DS register can be changed directly using
POP and LDS instructions. It points to the data segment memory where the
data is resided.

Stack Segment register: Stack segment (SS) is a 16-bit register containing

address of 64KB segment with program stack i.e the base address for the
Stack Segment. By default, the processor assumes that all the data
referenced by the stack pointer (SP) and base pointer (BP) registers is
located in the stack segment. SS register can be changed directly using POP
instruction. It is used for addressing stack segment of memory. The stack
segment is that segment of memory, which is used to store stack data.

Extra Segment register: Extra segment (ES) register is a 16-bit register

containing address of 64KB segment, usually with program data. ES holds
the base address for the Extra Segment. By default, the processor assumes
that the DI register references the ES segment in string manipulation
instructions. ES register can be changed directly using POP and LES
instructions. It also refers to segment which essentially is another data
segment of the memory. It also contains data.
Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 4
Introduction to Microprocessors, Module 1,Dept of CSE

Address Generation Circuit:

• The BIU has a Physical Address Generation Circuit.

• It generates the 20 bit physical address using Segment and Offset
addresses using the formula:
• Physical Address = Segment Address x 10H + Offset Address

6 Byte Pre-fetch Queue:

• It is a 6 byte queue (FIFO).

• Fetching the next instruction (by BIU from CS) while executing the
current instruction is called pipelining.
• Gets flushed whenever a branch instruction occurs.

2. The Execution Unit (EU):

Functions of EU

✓ Fetches instructions from the Queue in BIU, decodes and executes

arithmetic and logic operations using the ALU.
✓ Sends control signals for internal data transfer operations within the
microprocessor.
✓ Sends request signals to the BIU to access the external module.
✓ It operates with respect to T-states (clock cycles) and not machine
cycles.

The components of the EU are

❖ General purpose registers(GPRs)

❖ ALU
❖ Special purpose registers(SPRs)
❖ Instruction Register and Instruction Decoder(IR)
❖ Flag/Status Register(FR)

General purpose registers (GPRs)

• AX register: It holds operands and results during multiplication and

division operations. Also an accumulator during String operations.
Accumulator register consists of two 8-bit registers AL and AH, which
can be combined together and used as a 16- bit register AX. AL in this
case contains the low-order byte of the word, and AH contains the

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Introduction to Microprocessors, Module 1,Dept of CSE

high-order byte. Accumulator can be used for I/O operations, rotate

and string manipulation.
• BX register: It holds the memory address (offset address) in indirect
addressing modes. This register is mainly used as a base register. It
holds the starting base location of a memory region within a data
segment. It is used as offset storage for forming physical address in
case of certain addressing mode.
• CX register: It holds count for instructions like loop, rotate, shift and
string operations. It is used as default counter or count register in
case of string and loop instructions.
• DX register: It is used with AX to hold 32 bit values during
multiplication and division. Data register can be used as a port
number in I/O operations and implicit operand or destination in case
of few instructions. In integer 32-bit multiply and divide instruction
the DX register contains high-order word of the initial or resulting
number.

Special purpose registers (16-bit): The pointers contain within the

particular segments. The pointers IP, BP, SP usually contain offsets within
the code, data and stack segments respectively

• Stack Pointer: It is a 16-bit register to pointing to program stack in

the stack segment, which always Points the top of the stack. It is used
during the instructions like PUSH, POP, CALL, RET etc.
• Base Pointer: It is a 16-bit register pointing the data in stack
segment. BP can hold offset address of any location in the stack
segment. It is used to access random locations of the stack. BP
register is used for based, based indexed or register indirect
addressing.
• Source Index: It is a 16-bit register. It holds offset address in Data
Segment during string operations.SI is used for indexed, based
indexed and register indirect addressing, as well as a source data
addresses in string manipulation instructions.
• Destination Index: It is a 16-bit register and is used for indexed,
holds offset address in Extra Segment during string operations. It is
used in based indexed and register indirect addressing, as well as a
destination data addresses in string manipulation instructions.

Instruction Register and Instruction Decoder (IR):

The EU fetches an opcode from the queue into the instruction register. The
instruction decoder decodes it and sends the information to the control
circuit for execution.

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Introduction to Microprocessors, Module 1,Dept of CSE

Flag/Status register: It is 16 bit register as shown in the fig., only 9 flags

are defined to change or recognize the state of the microprocessor.

Fig: flag register

Status flags: Status flags are updated after every arithmetic and logic
operation.

1. carry flag(CF)
2. parity flag(PF)
3. auxiliary carry flag(AF)
4. zero flag(Z)
5. sign flag(S)
6. Overflow flag(OV)

Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a

carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary
to BCD conversion.

Parity Flag (PF): This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero
else it is reset.

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Introduction to Microprocessors, Module 1,Dept of CSE

Sign Flag (SF): In sign magnitude format the sign of number is indicated by
MSB bit. If the result of operation is negative, sign flag is set.

Control flags: The Control flags are used to control certain operations.
Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:

o trap flag(TF)
o interrupt flag(IF)
o direction flag(DF)

These flags can be set or reset using control instructions like CLC, STC,
CLD, STD, CLI, STI, etc.

Trap Flag (TF): It is used for single step control. It allows user to execute
one instruction of a program at a time for debugging. When trap flag is set,
program can be run in single step mode.

Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the

maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.

Direction Flag (DF): It is used in string operation. If it is set, string bytes

are accessed from higher memory address to lower memory address. When
it is reset, the string bytes are accessed from lower memory address to
higher memory address.

Arithmetic Logic Unit (16 bit): Performs 8 and 16 bit arithmetic and logic
operations.

PIN Diagram:

The pin diagram of 8086 is shown in the fig. Intel 8086 is a 16-bit HMOS
microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for
its operation. The 8086 uses 20-line address bus. It has a 16-line data bus.
The 20 lines of the address bus operate in multiplexed mode. The 16-low
order address bus lines have been multiplexed with data and 4 high-order
address bus lines have been multiplexed with status signals.

Pins 16-39: It is a multiplexed low order Address/Data bus (AD0-AD15).

These are address bus. When AD lines are used to transmit memory address
the symbol A is used instead of AD, for example A0-A15. When data are
transmitted over AD lines the symbol D is used in place of AD, for example
D0-D7, D8-D15 or D0-D15.

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Introduction to Microprocessors, Module 1,Dept of CSE

Pins 35-38(A16/S3, A17/S4, A18/S5, A19/S6): High order address bus

multiplexed with status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

Fig: 8086 pin diagram

Pin 34(BHE’/S7) : Bus High Enable/Status. During T1 it is low. It is used

to enable data onto the most significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data bus use BHE (Active Low) signal.
It is multiplexed with status signal S7. S7 signal is available during T2, T3
and T4.

Pin 33(MN/MX’): 8086 will work in two different modes. They are
Minimum/Maximum modes. MN/MX’=0: maximum mode and MN/MX’=1:
minimum mode.

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Introduction to Microprocessors, Module 1,Dept of CSE

Pin 32(RD’): This is used for read operation. It is an output signal. It is

active when low.

Pins 30-31(RQ’/GT1′, RQ’/GT0′): Request/Grant. These pins are used by

local bus masters used to force the microprocessor to release the local bus
at the end of the microprocessor’s current bus cycle. Each of the pin is bi-
directional. RQ’/GT0′ have higher priority than RQ’/GT1′.

Pin 29( LOCK’) : It is an active low pin. It indicates that other system bus
masters have not been allowed to gain control of the system bus while
LOCK’ is active low (0). The LOCK signal will be active until the completion
of the next instruction.

Pins 26-28(S2, S1, S0): Status pins. These pins are active during T4, T1
and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when
ready is inactive). These are used by the 8288 bus controller for generating
all the memory and I/O operation) access control signals. Any change in S2,
S1, S0 during T4 indicates the beginning of a bus cycle.

S2 S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state

Pins 24-25(QS1,QS0) : Queue Status. These signals indicate the status of

the internal 8086 instruction queue according to the table shown below

QS1 QS0 Status

0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue

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Introduction to Microprocessors, Module 1,Dept of CSE

Pin 23( TEST’) : This examined by a ‘WAIT’ instruction. If the TEST pin goes
low(0), execution will continue, else the processor remains in an idle state.
The input is internally synchronized during each of the clock cycle on
leading edge of the clock.

Pin 22(READY) : This is the acknowledgement from the memory or slow

device that they have completed the data transfer. The signal made available
by the devices is synchronized by the 8284A clock generator to provide
ready input to the microprocessor. The signal is active high(1).

Pin 21(RESET): This pin requires the microprocessor to terminate its

present activity immediately. The signal must be active high (1) for at least
four clock cycles.

Pin 20( GND) : Ground

Pin 19( CLK) : Clock Input. The clock input provides the basic timing for
processing operation and bus control activity. Its an asymmetric square
wave with a 33% duty cycle.

Pin 18(INTR): Interrupt Request. This is triggered input. This is sampled

during the last clock cycles of each instruction for determining the
availability of the request. If any interrupt request is found pending, the
processor enters the interrupt acknowledge cycle. This can be internally
masked after resulting the interrupt enable flag. This signal is active high(1)
and has been synchronized internally.

Pin 17(NMI): Non maskable interrupt. This is an edge triggered input which
results in a type II interrupt. A subroutine is then vectored through an
interrupt vector lookup table which is located in the system memory. NMI is
non-maskable internally by software. A transition made from low(0) to
high(1) initiates the interrupt at the end of the current instruction. This
input has been synchronized internally.

Pin 40 (Vcc): 8086 microprocessor requires +5.0 V D.C with a supply

voltage tolerance of ±10%. The 8086 uses a maximum supply current of 360
mA. Operate in ambient temperatures of between 32° F and 180° F. 80C86
is CMOS version that requires only 10 mA of power supply current and
function in temperature extremes of -40°F through +225° F.

Minimum mode pins (24-31): Minimum mode operation of the 8086 is

obtained by connecting the MN/ MX’ pin directly to +5.0 V. Do not connect
this pin to +5.0 V through a pull-up register, or it will not function correctly.

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Introduction to Microprocessors, Module 1,Dept of CSE

Pin 24(INTA’): It is an Interrupt acknowledgement signal in response to the

INTR input pin. This pin is normally used to gate the interrupt vector
number onto the data bus in response to an interrupt request. It is active
low (0) during T2, T3 and Tw of each interrupt acknowledge cycle.

Pin 25(ALE) : Address Latch Enable. ALE is provided by the microprocessor

to latch the address into the 8282 or 8283 address latch. It is an active
high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is
always integer.

Pin 26(DEN): Data enable. This pin is provided as an output enable for the
8286/8287 in a minimum system which uses transceiver. DEN is active
low(0) during each memory and input-output access and for INTA cycles.

Pin 27 (DT/R’): Data Transmit/Receive. This pin is required in minimum

systems that want to use an 8286 or 8287 data bus transceiver. The
direction of data flow is controlled through the transceiver.

Pin 28(M/IO’): The M/IO’ pin selects memory or I/O. This pin indicates
that the microprocessor address bus contains either a memory address or
an I/O port address. This pin is at its high-impedance state during a hold
acknowledge.

Pin 29(WR’): The write line is a strobe that indicates that the 8086 is
outputting data to a memory or I/O device. During the time that WR’ the is
a logic 0, the data bus contains valid data for memory or I/O. This pin floats
to a high impedance during a hold acknowledge.

Pin 30-31(HOLD/HOLDA): HOLD indicates that another master has been

requesting a local bus .This is an active high (1). The microprocessor
receiving the HOLD request will issue HLDA (high) as an acknowledgement
in the middle of a T4 or T1 clock cycle.

Physical Memory organization: 8088μP has 20 bit address bus hence it

can address total 220≈ 1M memory space (00000H-FFFFFH). 8088μP has 16
data line to carry the data even though each memory location holds only
1byte of data. If the data is 8 bits, 1M/C is sufficient to read/write the data.
But if the data is 16 bits, then it may take either 1 M/C or 2M/Cs
depending on the starting address of the word.

The total memory space of 8088μP i.e 220≈ 1M is divided in to two

independent banks of 512 KB size each as shown in the fig. Data bytes
associated with an even address (00000, 00002..., FFFFE) reside in the low
bank (even bank). Data bytes associated with an odd addresses (00001,
00003, ....., FFFFF) reside in the high bank (odd bank).

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Introduction to Microprocessors, Module 1,Dept of CSE

Address bits A1 through A19 are connected to both the banks to select the
location to be accessed. Bus low enable (BLE’) A0 and Bus high enable
(BHE’) are used as bank-select signals for lower and upper banks
respectively. Each of the memory banks provides half of the 16-bit data bus.
The even bank transfers data bytes over D0 -D7 data lines, while odd bank
use D8-D15 for data transfers.

The byte transfer operation and word transfer operations are as illustrated
in table below. The byte transfer operation needs one bus cycle, while word
transfer operation needs one or two bus cycles.

Address Data type BHE’ BLE’(A0) M/C

00000(even) Byte 1 0 1
00001(odd) Byte 0 1 1
00000(even) word 0 0 1
00001(odd) word 0/1 1/0 2

Case 1: to read/write a byte from /into a memory location in the even bank
whose address may be 00000H. Select BHE’=1 and since A0=0, even bank
will be selected and odd bank will be disabled, and a byte will be transferred
through D0 -D7 data lines.

Ex: MOV AH, DS; byte PTR (00000H)

Case 2: to read/write a byte from /into a memory location in the odd bank
whose address may be 00001H. Select BHE’=0 and since A0=1, odd bank will
be selected and even bank will be disabled, and a byte will be transferred
through D8 –D15 data lines.

Ex: MOV AL, DS; byte PTR (00001H)

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Introduction to Microprocessors, Module 1,Dept of CSE

Case 4: To read/write a word from/into the memory whose addresses such

as 00000(even). Since A0=0 even bank will be selected, and μP will generate
BHE’ signal as low hence high lower bank also selected. As both the banks
have individual data line, with in 1st M/C a word can be transferred.

MOV AX, DS; Word PTR(00000H)

Case 4: To read/write a word from/into the memory whose addresses such

as 00001(odd). Initially A0=1 hence even bank is disabled, at the same time
μP will grant BHE’=0 signal, hence the odd bank will be enabled for the 1st
M/C and a byte will be transferred through D8 –D15 data lines. During the
2nd M/C, 8088μP will send the address as 00002H, hence A0=0, and
processor will generate BHE’ signal is high, therefore even bank will be
selected, now the byte data transfer will be done through D0 –D7.

Ex: MOV AX,DS; word PTR(00001H)

Minimum mode of operation: Minimum mode operation is the least

expensive way to operate the 8086 microprocessor. It costs less because all
the control signals for the memory and I/O are generated by the
microprocessor. These control signals are identical to those of the Intel
8085A, an earlier 8-bit microprocessor. The minimum mode allows the
8085A 8-bit peripherals to be used with the 8086 without any special
considerations.

Fig: 8086 minimum mode of operation

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Introduction to Microprocessors, Module 1,Dept of CSE

8086 will take 4T states for IOR, IOW, MEMR and MEMW machine cycles.
µP will provide the address information in AD0-AD15 & A16-A19 line.

Read cycle: During the 1st T state of every machine cycle the ALE makes a
transition from low to high and again from high to low. With the trailing
edge of the ALE signal the address information is latched at the o/p of the
latch and will be there throughout the machine cycle. M/IO’ and DT/R’
settle down accordingly at the beginning of M/C and remains as it is
throughout the M/C. In read M/C, during T2 RD’ and DEN’ signals makes
transition from high to low and is continued throughout the M/C. During
the T3 µP just waits and in T4 it will draws RD’ and DEN’ signals and
whatever the data in the data bus takes it is valid data.

Fig. Read Machine cycle

Write cycle: During the 1st T state of write M/C the ALE makes a transition
from low to high and again from high to low. With the trailing edge of the
ALE signal the address information is latched at the o/p of the latch and will
be there throughout the machine cycle. M/IO’ signal will settle down and
DT/R’ signal makes a transition from low to high accordingly at the
beginning of the M/C and unchanged throughout the M/C. In write cycle,
during T2 the WR’ and DEN’ make transition from high to low as they are
active low signals. During the T3 µP just waits and in T4 it will draws WR’
and DEN’ signals and whatever the data in the data bus takes it is valid
data. If ready pin is low somewhere before end of T2 then at the end of T2 it
will be sampled by the processor and after T3 instead of generating T4 T
state processor will generate one wait state. During the wait state the status
of AB, DB and CBs remains unchanged and the READY pin is sampled by
the processor. If it is still low one more wait state is introduced. This
process will be continued until the READY pin is high. Once the READY pin
is high the processor will generate the T4 T state and ends the machine
cycle.

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Introduction to Microprocessors, Module 1,Dept of CSE

Fig: write machine cycle

Maximum mode of operation: µP will work in this mode with MN/MX’

pin=0. Maximum mode is used only when the system contains external
coprocessors such as 8087 arithmetic coprocessor and 8089 I/O
coprocessor. In this mode, the host processor and the coprocessors will
share the common property of system bus. Both 8087/8089 has their own
instruction set and capable of performing complex arithmetic operations
upon floating point data as well as several I/O operations. The program for
8086 and instructions of 8087/8089 can stay together in the main memory.
When it executed by a single processor in ALP, the 8087 instruction is
recognized as if the first letter is F. 8086 fetches the whole program and
bytes containing op-codes, addressing mode, address/data reaches the
instruction queue inside the processor. The same type also reaches the
queue of 8087. If the particular instruction is for 8086, then 8087 will treat
that instruction as NOP for him and vice versa.

Maximum mode operation differs from minimum mode in the way some of
the control signals must be externally generated. In the maximum mode
additional circuitry (8288-external bus controller to provide the signals
eliminated from the 8086 by the maximum mode operation, as there are not
enough pins on the 8086 for bus control during maximum mode) is required
to translate the control signals. This additional circuitry converts the status
signals (S2-S0) into the I/O and memory transfer signals. It also generates
the control signals required to direct the data flow and for controlling 8282
latches and 8286 transceivers. 8086 system that is operated in maximum
mode must have an 8288 bus controller. The fig illustrates the maximum
mode of 8086
In this mode, the processor derives the status signal S2, S1, S0.
Another chip called bus controller derives the control signal using this
status information.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 16

Introduction to Microprocessors, Module 1,Dept of CSE

Fig. Maximum mode of operation

Read cycle: maximum mode is a multiprocessor system, where the status

signals S2-S0 shows which system is activate and which system is
deactivated. These status signal will be active for the first 2 T states and
deactivated 2 T states and again

S2’S1’ S0’ CPU cycle 8288

command
0 0 0 Interrupt Acknowledgment INTA’
0 0 1 I/O read IORC’
0 1 0 I/O write IOWC’ AIOWC’
0 1 1 Halt none
1 0 0 Fetch MRDC’
1 0 1 Memory read MRDC’
1 1 0 Memory write MWTC’ AMWC’
1 1 1 Passive none

Queue Status
Qs1 Qs0 Q status
0 0 Queue is ideal
0 1 1st byte of the opcode
1 0 Queue is empty
1 1 Subsequent byte of queue

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 17

Introduction to Microprocessors, Module 1,Dept of CSE

Fig: memory read bus cycle

Write cycle:

8288 bus controller: Fig illustrates the block diagram and pin-out of the
8288 bus controller. The control bus developed by the 8288 bus controller
contains separate signals for I/O (IORC’ and IOWC’) and memory ( MRDC’
and MWTC’). Also contains advanced memory (AMWC) and I/O (AIOWC’)

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 18

Introduction to Microprocessors, Module 1,Dept of CSE

write strobes, and INTA’ signal. These signals replace the minimum mode
ALE,WR’,IO/M’, DT/R’,DEN’, and INTA’, which are lost when the 8086
microprocessors are operated in the maximum mode.

Fig: 8288 block diagram

S2-S0 Status inputs are connected to the status output pins

on the 8086 microprocessor. These three signals are
decoded to generate the timing signals for the system
CLK The clock input provides internal timing and must be
connected to the CLK output pin of the 8284A clock
generator.
ALE The address latch enable output is used to demultiplex
the address/data bus
DEN The data bus enable pin controls the bidirectional data
bus buffers in the system. This is an active high output
pin that is the opposite polarity from the DEN’ signal
found on the microprocessor when operated in the
minimum mode.
DT/R’ The data transmit/receive signal is output by the 8288
to control the direction of the bidirectional data bus
buffers.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 19

Introduction to Microprocessors, Module 1,Dept of CSE

AIOWC’/AMWC’ Advance I/O Write Command/Advance Memory Write

Command. These signals are similar to IOWC and
MWTC except that they are activated one clock pulse
earlier. This gives slow interfaces an extra clock cycle to
prepare to input the data.
AEN’ IOB CEN The control enable input enables the command output
pins on the 8288.

These pins are used in multiprocessor system. With a

single processor in the system, AEN and IOB are
grounded and CEN is tied high. AEN causes the 8288 to
enable the memory control signals. IOB (I/O bus mode)
signal selects either the I/O bus mode or system bus
mode operation. CEN (control enable) input enables the
command output pins on the 8288.
MCE/PDEN’ It controls the mode of operation of 8259. It selects
(Master Cascade cascade operation for 8259 (interrupt controller) if IOB
Enable/Peripheral signal is grounded and enables the I/O bus transceivers
Data Enable) : if IOB is tied high.
MRDC (Memory It instructs the memory to put the contents of the
Read Command) : addressed location on the data bus.
MWTC (Memory : It instructs the memory to accept the data on the data
Write Command) bus and load the data into the addressed memory
location.
IORC (I/O Read It instructs an I/O device to put the data contained in
Command) the addressed port on the data bus.
IOWC (I/0 Write It instructs an I/O device to accept the data on the data
Command) bus and load the data into the addressed port.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 20